積體電路測試最常用的模型為固定型錯誤模型 (stuck-at fault model)，主要原因在於固定型錯誤模型的設計簡單，不需要複雜的計算，就能得到不錯的測試結果。然而，若想要進一步分析積體電路內部為何會產生錯誤，固定型錯誤模型便顯得過於簡略，整體的偵錯能力一直無法提高，如果可以改良模型使得與真實情況接近，偵錯效能應該可以獲得改善。
要建立一與真實情況接近的模型，我們採用分析光罩佈局的方式，第一階段透過修改電路佈局來模擬生產過程所造成的瑕疵，第二階段進行電晶體層級的行為模擬得到瑕疵所造成的錯誤徵狀，第三階段用數位邏輯電路實現整個錯誤機制，並取代受瑕疵影響的電路。
我們將焦點放在橋接錯誤，觀察因瑕疵產生橋接錯誤時對電路造成的影響，並且利用新的模型評估拜占庭錯誤發生的機率。

The stuck-at fault model is popular due to its simplicity, and because it has proven to be effective both in providing high defect coverage when used as a fault model for test generation and when diagnosing a limited range of faulty behaviors. Our method uses the circuit layout to determine the relative probabilities of individual physical faults in the fabricated circuit. The concept is that a spot defect which is an area of extra conducting material that creates an unintentional electrical short in a circuit. A defect injector is described in this thesis. It can inject defect automatically and integrate the other tools to perform realistic bridging fault modeling and diagnosis.

[1] Yuming Gong, and S. Chakravarty, “Locating Bridging Faults Using Dynamically Computed Stuck-at Fault Dictionaries,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.17, no. 9, pp. 876 – 887, Sept. 1998.
[2] D.B. Lavo, B. Chess, T. Larrabee, and F.J. Ferguson, “Diagnosing realistic bridging faults with single stuck-at information,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 3, pp. 255 – 268, March 1998.
[3] S.D. Millman, and J.M. Acken, “Diagnosing CMOS bridging faults with stuck-at, IDDQ, and voting model fault dictionaries,” IEEE Custom Integrated Circuits Conference, pp. 409 – 412, May 1994.
[4] J. Segura, A. Keshavarzi, J. Soden, and C. Hawkins, “Parametric failures in CMOS ICs - a defect-based analysis,” IEEE International Test Conference, pp. 90 – 99, Oct. 2002.
[5] S. Chakravarty, K. Komeyli, E.W. Savage, M.J. Carruthers, B.T. Stastny, and S.T. Zachariah, “Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms,” IEEE VLSI Test Symposium, pp.367 – 372, April 2002.
[6] S.T. Zachariah, and S. Chakravarty, “Algorithm to Extract Two-Node Bridges,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 4, pp.741 – 744, Aug. 2003.
[7] F.M. Goncalves, I.C. Teixeira, and J.P. Teixeira, “Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 29 – 37, Oct. 1997.
[8] A.L. Jee, and F. J. Ferguson, “Carafe : An Inductive Fault Analysis Tool for CMOS VLSI Circuits,” IEEE VLSI Test Symposium, pp. 92 – 98, April 1993.
[9] P.K. Nag, and W. Maly, “Hierarchical Extraction of Critical Area for Shorts in Very Large ICs,” IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 19 – 27, Nov. 1995.
[10] F.M. Goncalves, I.C. Teixeira, and J.P. Teixeira, “Integrated Approach for Circuit and Fault Extraction of VLSI Circuits,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.96 – 104, Nov. 1996.
[11] Z. Stanojevic, and D.M.H. Walker, “FedEx – A Fast Bridging Fault Extractor,” IEEE International Test Conference, pp.696 – 703, Nov. 2001.
[12] ALBERT V. FERRIS-PRABHU, “Defect Size Variations and Their Effect on the Critical Area of VLSI Devices,” IEEE Journal of Solid-State Circuits, vol. 20, no. 4, pp. 878 - 880, Aug. 1985.
[13] D.B. Lavo, T. Larrabee, and B. Chess, “Beyond the Byzantine Generals Unexpected Behavior and Bridging Fault Diagnosis,” International Test Conference, pp. 611 - 619, Oct. 1996.
[14] Y.-C. Lin and S.-Y. Huang, "Chip-Level Diagnostic Strategy For Full-Scan Designs With Multiple Faults," Proc. of Asian Test Symposium, Nov. 2003.