時脈與資料回復電路(CDR)已經被廣泛應用在許多消費性電子產品之中。應用於串列傳輸的接收介面的話，在較低的頻率應用下，通常是採用數位電路來完成，常見的像是數位式鎖相迴路 (DPLL)。然而在一些較高速的應用上，例如光纖通訊系統，由於其傳輸的資料時脈頻率較高，所以通常都是用類比式電路來完成。對於單一通道動輒要達到數Gb/s範圍的收發器大部分是利用較昂貴的砷化鎵(GaAs)，矽鍺(SiGe)，雙載子電晶體(BJT)或BiCMOS製程來實現，其可操作頻率較高，對於雜訊抵抗能力較強，有比較好的性能，但是其缺點就是製程比較昂貴、整合不易且通常需耗掉較多的電流。近年來，CMOS的製程技術不斷的進步，因此CMOS CDR在學術期刊上廣為應用與發表，由於CDR電路常需要與其他電路做整合的動作，所以CMOS低耗電、低價格、易整合的優點應該是相當的適合需求，我們可以利用電路的技術來克服元件本身的缺點，進而達到SOC的目標。

本論文實作一個應用於光通訊SONET OC-48規格之CDR，希望以較便宜且高整合性之TSMC 0.35μm CMOS 2P4M製程來達到2.5Gb/s高速、高資料量的目標。吾人設計之CDR電路為半速架構，其中包含半速相位偵測器、半速頻率偵測器、充電泵、迴路濾波器以及壓控震盪器，震盪器之頻率操作在半速1.25GHz，降低了振盪器的設計難度。模擬結果，在不包含輸入輸出緩衝器操作在3.3V電壓下，功率消耗為107.7mW。量測結果發現，CDR電路可以鎖定在輸入為2.5Gb/s之週期性資料，晶片大小為1160 x 980μm2。

Clock and data recovery circuits (CDR) have already been applied in a lot of consumption electronic products. The ones that applied to serial data communications, under the circumstances that lower data rate, CDR circuits are usually realized by digital circuits, such as digital type phase-locked loop (DPLL). On some high-speed applications, such as optical fiber communication systems, because the data rate is relatively high, so CDR circuits are usually implemented by analog circuits. For transceivers which reach Gb/s are usually realized by GaAs, SiGe, BJT and BiCMOS, because their operate frequency can be relatively high, and have better immunity for noise. But they usually spend large power consumption, beside are expensive and not suitable for integration. In recent years, the CMOS technologies progress constantly, so CMOS CDR is used and issued far and wide at the academic periodical. Because CDR circuits are often needed for integrated with other circuits, so CMOS which is low power consumptive, low cost and high integrating is very suitable for reaching the goal of SOC.

A 2.5Gb/s half-rate CDR circuit for SONET OC-48 application is presented in this thesis, including half-rate phase detector, half-rate frequency detector, charge pump, loop filter and voltage-controlled oscillator. Under the half-rate architecture, the frequency of voltage-controlled oscillator must operate in 1.25GHz, therefore we reduce the design difficulty of voltage-controlled oscillator. We hope that the CDR circuit can be realized by TSMC 0.35μm 2P4M CMOS process which is cheap and high integration to reach high-speed and high-capability applications. Simulation results show that this CDR circuit operating under 3.3V, the power consumption is 107.7mW (without I/O buffers).Measurement results show that the CDR circuit can lock under periodic 2.5Gb/s data, and the chip size is 1160 x 980μm2.

參考文獻
[1] Y. M. Greshishchev and P. Schvan, “SiGe clock and data recovery IC with linear type PLL for 10-Gb/s SONET application,” in Proc. 1999 Bipolar/BiCMOS Circuits and Technology Meeting, Sept. 1999, pp.169-172.
[2] M. Wurzer et al., “40-Gb/s integrated clock and data recovery circuit in a silicon bipolar technology,” in Proc. 1998 Bipolar/BiCMOS Circuits and Technology Meeting, Sept. 1998, pp.136-139.
[3] H Ransijn and P. O’ Connor, “A PLL-Based 2.5Gb/s GaAs clock and data regenerator IC,” IEEE J. Solid-State Circuits, vol. 26, no.10, Oct. 1991.
[4] 楊素華, 陳憶婷, 簡昕慧, 張詩意, 楊筑閔, ” 光纖通訊技術發展現況,” 科學發展月刊, 第29卷, 第12期, pp. 879-883, 中華民國九十年十月.
[5] Jae Shin Lee; Woo Kiang Jin; Dong Myung Choi; Bang-Wen Lee; Suki Kim, “A wide range PLL for 64X speed CD-ROM & 10X speed DVD-ROM,” Consumer Electronics, 2000. ICCE. 2000 Digest of Technical Papers. International Conference on, 2000 Page(s):98-99
[6] Http://www.agilent.com, Jitter Analysis Techniques for High Data Rate, Application Note 1432.
[7] Rich Walker, “Clock and Data Recovery for Serial Digital Communication focusing on bang-bang loop CDR design methodology,” ISSCC Short Course, February 2002.
[8] Jri Lee, Behzad Razavi, “A 40-Gb/s Clock and Data Recovery Circuit in 0.18-μm CMOS Technology, “ IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2181-2190, December 2003.
[9] Seong-Jun Song, Sung Min Park, Hoi-Jun Yoo, “A 4-Gb/s CMOS Clock and Data Recovery Circuit Using 1/8-Rate Clock Technique,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1213-1219, July 2003.
[10] http://www.ee.cgu.edu.tw/member/teacher/rjyang/rjyang_index.htm
[11] Behzad Razavi, “Design of Integrated Circuits for Optical Communications,” McGRAW-HILL, International Edition 2003.
[12] Y. Moon, D.-K. Jeong, and G. Ahn, “A 0.6-2.5 Gbaud CMOS tracked 3x oversampling transceiver with dead-zone phase detection for robust clock/data recovery,” IEEE J. Solid-State Circuits, vol. 36, NO.12, pp. 1974-1983, Dec. 2001.

[13] F. Herzel and B. Razavi, “A Study of Ocillator Jitter Due to Supply and Substrate Noise,” IEEE Trans. Circuits and Systems, Part II, vol. 46, pp. 56-62, Jan. 1999.
[14] J. A. McNeil, “Jitter in Ring Oscillators,” IEEE Journal of Solid-State Circuits, vol. 32, pp- 870-879, June 1997.
[15] Lu Jianhua; Tian Lei; Chen Haitao; Xie Tingting; Chen Zhiheng; Wang Zhigong, “Design Techniques of CMOS SCL circuits for Gb/s Applications,” ASIC, 2001. Proceedings. 4th International Conference on 23-25 Oct. 2001 Page(s):559-562.
[16] 張耿孟, “應用於W-CDMA之整數型頻率合成器,” 國立清華大學, 電子工程研究所, 碩士論文, 中華民國九十三年六月.
[17] Jafar Savoj, Behzad Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector,” IEEE Journal of Solid-State Circuits, vol. 36, no. 5, pp. 761-767, May 2001.
[18] Jafar Savoj, Behzad Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Binary Phase/Frequency Detector,” IEEE Journal of Solid-State Circuits, vol. 38, no. 1, pp. 13-21, January 2003.
[19] Joonsuk Lee, Beomsup Kim, “A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control,” IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp. 1137-1145, August 2000.
[20] Rong-Jyi Yang, Shang-Ping Chen, Shen-Iuan Liu, “A 3.125-Gb/s Clock and Data Recovery Circuit for the 10-Gbase-LX4 Ethernet,” IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp.1356-1360, August 2004.
[21] Seon-Jun Lee, Beomsup Kim, Kwyro Lee, “A Novel High-Speed Ring Oscillator for Multiphase Clock Generation Using Negative Skewed Delay Scheme,” IEEE Journal of Solid-State Circuits, vol. 32, no. 2, pp. 289-291, February 1997.
[22] Chan-Hong Park, Beomsup Kim, “A Low-Noise, 900-MHz VCO in 0.6-μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 586-591, May 1999.
[23] Kiyoshi Ishii, Keiji Kishine, Haruhiko Ichino, “A Jitter Suppression Technique for a 2.48832-Gb/s Clock and Data Recovery Circuit,” IEEE Transactions on Circuits and Systems II, vol. 49, no. 4, pp. 266-272, April 2002.
[24] J. Christoph Scheytt, Gerhard Hanke, Ulrich Langmann, “A 0.155-, 0.622-, and 2.488-Gb/s Automatic Bit-Rate Selecting Clock and Data Recovery IC for Bit-Rate Transparent SDH Systems,” IEEE Journal of Solid-State Circuits, vol. 34, no. 12, pp. 1935-1943, December 1999.

[25] Rong-Jyi Yang, Shen Iuan Liu, “A Fully Integrated 1.7-3.125Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector,” IEICE Trans. Electron, vol. E88-C, no. 8, pp. 1726-1730, August 2005.
[26] Http://www.agilent.com, Calibrated Jitter, Jitter Tolerance Test and Jitter Laboratory with the Agilent J-BERT N4903A, Application Note.
[27] Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” McGRAW-Hill international edition, 2001.