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研究生: 翁梓洋
Wong, Zih-Yang
論文名稱: 具有數位自動增益迴路之2.4-GHz無電感式射頻前端
A 2.4-GHz Inductorless RF Front-End with Digital Automatic Gain Control Loop
指導教授: 謝志成
Hsieh, Chih-Cheng
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2010
畢業學年度: 98
語文別: 英文
論文頁數: 100
中文關鍵詞: 無電感射頻前端自動增益迴路
外文關鍵詞: Inductorless, RF Front-End, AGC
相關次數: 點閱:2下載:0
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  • 本篇論文的主要目的在於設計一個應用在2.4-GHz ISM 頻段之可變增益的射頻前端電路。為了節省晶片面積,我們採用一個共閘極架構並使用電阻當做負載的低雜訊放大器的設計,藉此避免在晶片內使用螺旋形的電感。在低雜訊放大器及混波器內,我們把負載利用數位訊號來控制調整以達到總共8個增益級。而藉由設定增益與輸入訊號功率成反比,射頻前端電路的輸出範圍將會被減小。因此可減輕該電路對線性度的需求。
    此外,一個包含峰值探測器、比較器和數位控制電路的自動增益控制迴路被應用與整合進此射頻前端電路,用來適當的設定射頻前端電路的增益大小。峰值探測器可以測得經由射頻電路後所放大訊號的振幅大小,並將其轉換成一直流電壓值。接下來將此直流電壓值與參考電壓來做比較後,再利用數位控制電路來決定增益該如何變化並落在所欲的範圍內。當輸出訊號位於所欲的大小範圍或在最大、最小增益情況時,此時自動增益控制迴路將會被關閉。因此,自動增益回授控制迴路並不會影響射頻前端電路的雜訊表現。
    本論文內所有電路皆使用臺灣積體電路制造股份有限公司 0.18-μm mixed-mode 互補式金屬氧化物半導體製程實現,此具有自動增益控制的射頻前端電路其晶片面積為1.0 × 1.0 mm2。 根據量測的結果,增益控制範圍可從-4.1 dB至14.62 dB共8個增益級,而其步進增益約為2.7 dB。在最大增益設定下射頻前端電路的NF在 10 MHz為8.79 dB,而在最小增益設定下射頻前端電路的P1dB 可達到-17 dBm。在1.8伏特的電壓下,整個晶片包含輸出緩衝電路的功率消耗為21 mW。


    In this thesis, a variable gain RF front-end circuit is designed for 2.4-GHz ISM band applications. In order to reduce the chip area, a common-gate LNA with a resistor load is adopted to avoid any use of on-chip spiral inductors. Both loads of the LNA and mixer are digitally controllable so that there are totally 8 gain states. By setting the gain inverse proportional to RF input power, the output dynamic range of the RF front-end circuit is reduced. Therefore, the circuit linearity requirement is relaxed.
    To set the RF front-end gain appropriately, an automatic gain control (AGC) loop is integrated with the RF front-end circuit. It consists of a peak detector, a comparator and a digital control logic circuit. The amplitude level of IF signal is transformed to a DC voltage by the peak detector. This DC voltage is compared with a reference voltage to decide the gain setting. When the IF amplitude level is located at the desired range or the RF frontend gain is maximum or minimum, the AGC loop is disabled. Therefore, the noise performance of the RF front-end is not affected by the AGC loop.
    All designed circuits are realized in TSMC 0.18-μm mixed-mode CMOS technology and the chip area of the RF front-end with AGC is 1.0 × 1.0 mm2. According to the measurement results, the total gain range is around -4.1 ~ 14.62 dB with 2.7-dB gain step. The noise figure for the maximum gain setting is 8.79 dB. The P1dB for the minimum gain setting is -17 dBm. The total power consumption including the output buffer is 21 mW under a 1.8-V power supply.

    Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organizations 3 Chapter 2 Architecture of RF Front-End with AGC 4 2.1 Introduction 4 2.2 RF Front-End Overview 4 2.2.1 Receiver Architectures 4 2.2.2 RF Front-End Specifications 8 2.3 Proposed RF Front-End with AGC 13 2.3.1 Overall Architecture 13 2.3.2 AGC Loop Behavior 15 2.4 Summary 16 Chapter 3 Variable Gain LNA and Mixer Design 17 3.1 Introduction 17 3.2 MOSFET Noise Optimization 17 3.2.1 MOS Noise Model 17 3.2.2 Theoretic Noise Analysis and Simulation 20 3.3 Variable Gain LNA 27 3.3.1 LNA Input Stage 29 3.3.2 Cascode Current Amplifier with Negative Gm 33 3.3.3 Gain Control Circuit 37 3.3.4 Bias Circuit 38 3.4 Active Down Conversion Mixer and Buffer 40 3.4.1 Proposed Down Conversion Mixer 40 3.4.2 LO and IF Buffer 42 3.5 Simulation Results 43 3.5.1 LNA and Mixer 43 3.5.2 RF Front-End 45 3.5 Summary 50 Chapter 4 Automatic Gain Control Loop Design 51 4.1 Introduction 51 4.2 Peak Detector and Comparator 51 4.3 AGC Digital Feedback Loop 55 4.4 Simulation Results 59 4.5 Summary 62 Chapter 5 AGC RF Front-End Implementation and Measurement Results and Design Improvement 63 5.1 Mix-Mode Simulation of RF Front-End with AGC 63 5.2 Measurement of RF Front-End with AGC 68 5.2.1 Measurement Setup 68 5.2.2 Measurement Results 70 5.3 Improve of Gain Control Circuit 91 5.4 Summary 96 Chapter 6 Conclusions and Future Work 97 6.1 Conclusion 97 6.2 Future Work 97 BIBLOGRAPHY: 98

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