基於IEEE 1500之自動化延遲錯誤測試架構｜國立清華大學博碩士論文庫

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研究生：	林志韋 Jhih-Wei Lin
論文名稱：	基於IEEE 1500之自動化延遲錯誤測試架構 An Automatic Delay Fault Test Framework based on IEEE 1500
指導教授：	張慶元 Tsin-Yuan Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 產業研發碩士積體電路設計專班 Industrial Technology R&D Master Program on IC Design
論文出版年：	2007
畢業學年度：	95
語文別：	中文
論文頁數：	47
中文關鍵詞：	延遲錯誤測試
外文關鍵詞：	Delay Fault Testing
相關次數：	點閱：1 下載：0
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在半導體產業的高度發展之下，晶片中所擁有的電晶體個數隨著製程技術的提升表現出一個快速成長的趨勢，也使後原本只擁有單一功能的晶片可以將一個完整的系統置入其中，也就是所謂的系統晶片(System on Chip)。而系統晶片的運用也漸漸變成一個成熟的技術，且隨著操作頻率的提升，許多與時間有關的問題以及所造成的錯誤也變的越趨嚴重，其中將針對因延遲所造成的錯誤做一個討論，我們稱之為延遲錯誤測試(Delay Fault Testing)，對系統晶片而言，目前已有一套關於系統晶片測試的標準存在，但在這套標準當中並未對延遲錯誤測試制定出一套規範，為了使用整個系統晶片測試標準更加的完善，試圖在這套標準之下將延遲錯誤測試的功能置入其中，為了達到這個目的，文中提出了一個時脈控制器來產生延遲錯誤測試所需要的連續的系統時脈，並以一套完善的流程來完成整個延遲錯誤測試，並驗證其正確性以確保整個測試的可靠度及準確性。

Due to the rapidly increasing capacity of semi-conductor technology, the design methodology has come to a higher level of abstraction. The IEEE 1500 is provided to test functionality of each core in SOC but dose not verify its timing specifications. In this thesis, a delay fault test architecture that consists of modified wrapper based on IEEE 1500, a delay-test-aware clock controller and the modified TAP controller are presented. The delay-test-aware clock controller can generate the desired clock pulse for delay fault timing specification. Then, the test sequence is controlled by the modified TAP controller. The simulation results show successful delay fault testing application to a Crypto Processor with satisfying test quality and accuracy.

誌謝……………………………………………………………………    I
Abstract………………………………………………………………..    II
中文摘要………………………………………………………………    III
目錄……………………………………………………………………    IV
List of Contents………………………………………………………..    XI
List of Figures…………………………………………………………    XIII
List of Tables………………………………………………………......    XV
Chapter 1.  Introduction……………………………………………...    1
Chapter 2.  Preliminary…….………………………………………...    5
      2.1 IEEE 1500 Overview………….…………………………    5
2.1.1 Core Test Language…………………..……………    5
2.1.2 Scalable Core Test Architecture……………………    6
        2.2 Requirement and Delay Test Schemes…...………………    8
2.3 Previous Works…………………………………………..    10
2.3.1 DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs[12]…………………………..    10
2.3.2 Clock Pulse Filter………………………………….    14
Chapter 3.  Modification……………………………………………..    18
       3.1 Wrapper Boundary Register…...…………………………    19
3.1.1 Input WBR Modification………………………….    20
3.1.2 Output WBR Modification………………………...    21
       3.2 Synchronous Control…………………………….……….    23
       3.3 Clock Controller……………………………………….…    24
3.3.1 Clock gating and switching circuit………………...    25
3.3.2 The Control Cell…………………………………...    26
3.3.3 Proposed Clock Controller………………………...    29
       3.4 The TAP Controller…..……………………………….…    30
       3.5 Explanation of Delay fault testing sequence….……….…    33
Chapter 4.  Delay Fault Test Based on IEEE 1500…………………..    37
       4.1 The Proposed Architecture…….…………………………    37
       4.2 Estimated Test Application Time………………………...     39
Chapter 5.  Simulation Results……………………………………….    41
Chapter 6.  Conclusions & Future Works……………………………        44
       6.1 Conclusions………………………………………………    44
       6.2 Future Works……………………………………………..    45
Bibliography…………………………………………………………..    46

                                

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[16] P.-L Chen, H.-H Chiu and T.-Y Chang, “A New Delay Fault Testing Framework on Core-Based System-on-chip,” Proc. of Workshop on RTL and High Level Testing, pages 33-40, November 2006.

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