當電晶體微縮到低於20 nm 以下，傳統的MOSFET會出現次臨界漏電流、閘極漏電流等的問題。這些問題可以藉由鰭式電晶體的結構克服。鰭式電晶體有較好的電特性，因其通道外型高而薄。本論文主要應用氫電漿及高溫處理的效應。氫電漿作用在矽表面，有輕微蝕刻的效果，有助於使通道側壁垂直，名為trimming，可提高電晶體電特性。再者，矽經過高溫處理，通道上層趨圓滑，能降低尖端放電，使電特性提升。
第一部分，主要為利用實驗室之前成功建立的一套SOI n-FinFET標準製程。Trimming在矽鰭式電晶體的矽通道上，並改變不同氫氣電漿處理時間，來得到較垂直的結構做探討。整體S.S維持在65~75 mV/dec之間。300sec的氫氣trimming處理元件的電特性較標準元件提升。另一方面，使用1200sec的氫氣trimming處理元件的電性反而會下降。例如，300sec的氫氣trimming處理元件閘極漏電流密度約2.94x10-7 A/cm2、轉導值約32 µA/V及載子最大遷移率約413 cm2/V-sec。標準式片及300sec的氫氣trimming處理元件表現良好，臨界電壓飄移特性的表現都維持在25mV左右。1200sec的氫氣trimming處理元件臨界電壓飄移量則會稍大。
第二部分，為利用不同高溫處理之方式試圖使上層通道越趨圓滑。實驗結果發現，隨著通道處理溫度的增加，電性得以改善。整體S.S維持在60~70 mV/dec之間，可見元件整體閘極控制能力表現不錯。使用高溫處理900℃之元件之元件的可達最低的次臨界擺幅最低約64.3 mV/dec、最低閘極漏電流密度約3.13x10-8 A/cm2、最大汲極電流約8.9x10-5 μA/μm、最大轉導值約114.7μA/V 及載子最大遷移率約488 cm2/V-s。再者，在可靠度方面，經過加壓後的高溫處理900℃之元件臨界電壓飄移量最小。其餘元件在臨界電壓飄移較大。

When transistors’ feature sizes scale down lower than 20 nm, conventional MOSFET confront some issues such as the effects of subthreshold leakage, gate leakage, and so on. These issues can be resolved by FinFET structure. The electrical characteristics of FinFET can be bettter if its channel shape is high and thin. Effects of hydrogen plasma and high temperature treatment are studied in this thesis. When hydrogen plasma treatment is aplied on silicon surface, a slight etching could make channel more vertical, namely trimming, and enhances electrical characteristics of device. Moreover, when a high temperature treatment is applied on silicon, channel surface would become smoother, which reduces corona discharge and improves electrical characteristics.
In the first part, SOI n-FinFET is successfully fabricated based on our previous work. A trimming process on silicon channel of FinFET is studied with different time of hydrogen plasma treatements to get a more vertical structure. Results show that subthreshold swing values of all devices are about 65 to 75 mV/dec. Electrical characteristics of device with 300 s trimming are better than those of control one. On the contrary, device with 1200 s trimming show worse performance. Device with 300 s trimming has better performance, demonstarting such as, gate leakage of about 2.94x10-7 A/cm2, transconductance of 32 μA/V and peak carrier mobility of 413 cm2/V-sec. Reliability characteristics of control sample and devices with 300 s trmming are good, showing threshold voltage shift of about 25 mV. Device with 1200 s trimming suffers a much higher threshold voltage shift.
In the second part, in order to continuously promote device characteristics, a high temperature treatment on FinFET is applied to make channel shape smoother. Experimental results show that electrical characteristics are improved with increasing treatment temperature. All samples show subthreshold swing values of about 60 to 70 mV/dec, indicating good gate control capability. Devices with 900℃ treatment have lowest subthreshold swing of 64.3 mV/dec, lowest gate leakage of 3.13x10-8 A/cm2, highest on current of 8.9x10-5 μA/μm, highest transconductance of 114.7μA/V and highest carrier mobility of 488 cm2/V-sec. Moreover, for reliability characteristics, device with 900℃ treatment performs a smaller threshold voltage shift after stressing. The other devices perform higher threshold voltage shifts.

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