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研究生: 陳維新
Wei-Hsin Chen
論文名稱: 單一多晶架構快閃記憶體之製造與研究
Studies on the Fabrication and Analysis of Single Poly Flash Memory
指導教授: 黃惠良
Huey-Liang Huang
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2005
畢業學年度: 93
語文別: 英文
論文頁數: 54
中文關鍵詞: 單一多晶快閃記憶體
外文關鍵詞: Single poly, Flash
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  • 非揮發性記憶體隨著消費性電子產品的蓬勃發展,應用的範圍也越來越廣泛特別在最近幾年受到手機、隨身碟、MP3及電玩的影響更是造成了大量的需求.其中所謂的快閃記憶體更是大受歡迎,因此大家競相投入製造。而近年來製程技術愈來愈進步也使的記憶體容量也愈作愈大,成本與容量是業界一致的考量。在此狀況下單一多晶架構快閃記憶體在漸漸受到大家的注意。一般快閃記憶製程通常為雙多晶結構 (double poly),比起一般邏輯製程光罩成本較高製造時間較長,相較之下單晶結構的優點就淺而易見。其優點如下 : (1) 用一般邏輯製程即可製造, (2) 光罩數量較少, (3) 製程步驟較少,(4) 製程可靠度較高 綜合以上各點成本為單一多晶架構快閃記憶體最大的優勢。雖然如此, 單晶結構也有其不足之處 :(1)其面積較堆較大,對於高密度記憶體的應用較為不利 (2) 重複讀寫的能力相對於雙多晶結構,仍顯不足。
    本論文是以0.25um 1P5M邏輯製程製造出單一多晶架構快閃記憶體,探討其不同面積之寫入及抹除效率,並粹取出浮動閘之耦合參數。實驗顯示: 它可提供優良的寫入及抹除效率並且可有效地應用耦合參數曲線作最佳化結構設計。另外RPO 光罩的應用,有效的提昇單一多晶架構快閃記憶體在 Salicide 製程的可靠度。綜何以上優點,若再稍作改善,相信不久的將來必可在記憶體市場中佔一席之地。


    Non-Volatile Memory has been developed for a long time. It is more attractive in these days because the flash is necessary for more and more consumer application. Now, some structures of Non-volatile memory were invented like Split gate flash and stack gate flash and they are popular in production. They are fabricated with double poly process which is special for flash .It is more expense than the general CMOS process because of the longer process turn around time, lower yield and higher cost.
    In this thesis, single poly flash cell is introduced .It is CMOS compatible and available for technology of 0.25 um logic single poly process without any process change. Fowler Nordheim tunneling and Channel Hot Carrier injection are used in this structure. There are excellent performances of program and erase and useful duration ability. Besides, a good couple ratio trend is extracted from experiment and it can be the reference of cell size design and the correction reference of simulation. And a new application of RPO mask is reported. RPO mask improve the salicide process to prevent from the leakage path induced by the salicide.
    Single poly cell can be used in OPT or MTP application and will be widespread used for design-in step and replacing the mask Rom to shorter the turn-around time because of its low cost and logic CMOS compatible.

    Contents Chapter 1. Introduction 1-1 Flash memories overview 1-2 Single poly flash memory introduction 1-3 Motivation of this study 1-4 Figure captions Chapter 2. Experiment of Cell fabrication 2-1. Process introductions 2-2. Cell structure 2-3. Cell size split 2-4. Introductions of RPO 2-5. Figure captions Chapter 3. The discussion of Program and Erase operation 3-1. Introduction of Hot carrier injection 3-2. Introduction of Fowler Nordheim Tunneling 3-3. Operation introduction of Single poly flash memory 3-4. Figure captions Chapter 4. Characteristic measurement and Discussion 4-1. Bias range definition of the cell operation 4-2. Measurement result of type 1 (Cp > Cn) 4-3. Measurement result of type 2 (Cp < Cn) 4-4. Couple ratio extraction 4-5. Endurance and Data retention 4-6. Figure captions Chapter 5. Simulation with SPICE tool 5-1.Threshold simulations and Couple Ratio extractions from simulation Result 5-2. Figure captions Chapter 6. Conclusion References

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