相對於其他類型的隨機存取記憶體而言，動態隨機存取記憶體結構簡單、高密度且相對便宜，在整個電腦架構設計上通常會將其當做主記憶體使用，然而，許多年來，降低存取記憶體的速度不如處理器時脈增加的快速，換句話說，動態隨機存取記憶體效率的演進相對於晶片核心時脈演進的速度來的慢許多，因此W. Wulf 和 S. McKee 就提出"記憶體牆"的概念。

因此，近幾十年來人們不再盲目的追求時脈高的單核心晶片，而是去增加單一晶片上的核心數或者使用網路多核心系統的概念增加平行度來達到降低功耗和增加產出效率。但不幸的是對於記憶體吞吐量的需求不減反增，因此許多科學家致力於改善記憶體存取效率，如：改善記憶體控制器的排程效率或者增加會流排的寬度來改善存取速度等等。

近年來，堆疊記憶體架構的出現縮短了處理器和記憶體之間速度的差距，但對於使用晶片網路的多核心系統架構來說，從處理器到到記憶體控制器的距離會隨著晶片上的網路越來越大而相對變遠，因此，基於這個原因，我們利用一個額外的多對多交換網路並且分組處理器提供一些額外的通道去處理多核心對記憶體控制器的存取，能夠減少因大量存取所造成的晶片網路壅塞，且能夠提升核心存取記憶體控制器的效率。經由SPLASH-2的實驗證明，可以將能使核心到記憶體的存取效率達到 1.02 到 1.13 倍。

Because the advantage of DRAM is its structural simplicity: high densities and more inexpensive than other type of RAM, it is very suited to be a role of main-memory in computer architecture. However, for many years, DRAM access latencies have not decreased at the same rate as microprocessor cycle times. In other words, the rate of improvement in processor speed exceeds the rate of improvement in DRAM memory speed, that W. Wulf and S. McKee called the phenomenon "memory wall". Therefore, in past few decades, people do not blindly upgrades single processor’s performance, but increasing the amount of on-chip cores or using the NoC-based many-core architecture for the throughput and low power consumption. Unfortunately, the demand for memory bandwidth or throughput is still increased. Therefore, many engineers dedicate to improve the efficiency between memory controller and DRAM by proposing better memory scheduling policy, increasing bandwidth and improving the access speed, etc. Recently, the emergence of 3D-stacked DRAM (wide I/O) slightly reduces the speed gap between processor and memory system. But the many-core architecture which use mesh or torus architecture a bridge to connect processors and memory controllers has a characteristic that some DRAM request from processor may go through very far distance to access memory controller. Based on the above motivation, we present an architecture which improves the efficiency of accessing stacked memories and reduce routing time on many-core platform. We use an extra crossbar switch interconnect to transport the DRAM request and groups few numbers of processor to specify DRAM-channel. We call the traditional method as \textbf{Original approach} and call our proposed architecture as \textbf{CS-based approach}. Experimental results of SPLASH2 applications demonstrates speed up that ranges from 1.02 to 1.13 times, with crossbar switch interconnect.

[1] Baas, B., Zhiyi Yu, Meeuwsen, M., Sattari, O., Apperson, R., Work, E., Webb, J., Lai,
M., Mohsenin, T., Truong, D., Cheung, J., \Asap: A ne-grained many-core platform
for dsp applications." IEEE Micro, pp. 27(2): 25{35, Mar. 2007.
[2] S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif,
L. Bao, J. Brown et al., \Tile64-processor: A 64-core soc with mesh interconnect," in
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE
International. IEEE, 2008, pp. 88{598.
[3] Vangal, S.R. et al., \An 80-tile sub-100-w tera
ops processor in 65 nm cmos." IEEE
Journal of Solid-State Circuits, pp. 43(1): 29{41, Jan. 2008.
[4] Mattson, T.G., Van Der Wijngaart, R., Frumkin, M., \Programming the intel 80-core
network-on-a-chip terascale processor."
[5] Howard, J., Dighe, S., Vangal, S.R., Ruhl, G., Borkar, N., Jain, S., Erraguntla, V.,
Konow, M., Riepen, M., Gries, M., Droege, G., Lund-Larsen, T., Steibl, S., Borkar,
S., De, V.K., Van Der Wijngaart, R., \A 48-core ia-32 processor in 45 nm cmos using
on-die message-passing and dvfs for performance and power scaling." IEEE Journal of
Solid-State Circuits, pp. 46(1): 173{183, Jan. 2011.
[6] Mattson, T.G., van der Wijngaart, R.F., Riepen, M., Lehnig, T., Brett, P., Haas, W.,
Kennedy, P., Howard, J., Vangal, S., Borkar, N., Ruhl, G., Dighe, S., \The 48-core sccprocessor: the programmer's view)," in Proc. Int. Conf. High Performance Computing,
Networking, Storage and Analysis (SC), pp. 1-11.
[7] W. A. Wulf and S. A. McKee, \Hitting the memory wall: implications of the obvious,"
ACM SIGARCH computer architecture news, vol. 23, no. 1, pp. 20{24, 1995.
[8] Manoj, S., Kanwen Wang, Hantao Huang, Hao Yu, \Smart I/Os: a data-pattern aware
2.5D interconnect with space-time multiplexing," in System Level Interconnect Predic-
tion (SLIP), 2015 ACM/IEEE International Workshop on, Jun. 2015, pp. 1{6.
[9] Dongjun Xu, Ningmei Yu, Sai Manoj, P.D., Kanwen Wang, Hao Yu, Mingbin Yu,
\A 2.5-D Memory-Logic Integration With Data-Pattern-Aware Memory Controller," in
Design & Test, IEEE (Volume:32, Issue: 4 ), Jun. 2015, pp. 1{10.
[10] G. H. Loh, \3D-stacked Memory Architectures for Multi-Core Processors," in ACM
SIGARCH Computer Architecture News, vol. 36, no. 3. IEEE Computer Society, 2008,
pp. 453{464.
[11] G. L. Loi, B. Agrawal, N. Srivastava, S.-C. Lin, T. Sherwood, and K. Banerjee, \A
thermally-aware performance analysis of vertically integrated (3-D) processor-memory
hierarchy," in Proceedings of the 43rd annual Design Automation Conference. ACM,
2006, pp. 991{996.
[12] Loi, Igor and Benini, Luca, \An ecient distributed memory interface for many-core
platform with 3D stacked DRAM," in Proceedings of the Conference on Design, Au-
tomation and Test in Europe. European Design and Automation Association, 2010,
pp. 99{104.
[13] Tao Zhang, Cong Xu, Ke Chen, Guangyu Sun, Yuan Xie, \3D-SWIFT: A High-
Performance 3D-Stacked Wide IO DRAM," in the ACM Great Lakes Symposium on
VLSI (GLSVLSI), May 2014.
52