BCD製程技術集合了BJT、CMOS與DMOS等電晶體元件在同一晶片上，同時可以維持各自的優點。本篇論文利用製程與電性模擬軟體分析不同佈局對0.25um BCD製程中BJT元件電流增益與電性的影響，進而設計高電流增益的BJT元件。再藉由實際下線的機會，選取模擬之元件作為下線的結構。而從實際元件結構量測與電性分析所得到的結果可知，確實實現了能提高電流增益的BJT元件結構，改善其放大特性。此外，也使用模擬軟體設計出具有良好的導通與放大特性之N通道JFET元件，再經由實際下線，成功的將N通道JFET元件結構整合於0.25um BCD製程中，提供電路設計者更多元件選擇性，也能利用JFET元件的優點，整合在晶片上，提高整體電路的效能。

The BCD process technology combines the BJT, CMOS, and DMOS transistors into the same chip and integrates their advantages. In this thesis, we use the simulation software of process and electricity to analyze the influence of different layout on current gain and electricity of BJT in 0.25um BCD process, and further design the BJT device with high current gain. By having the chance of actual tapeout, some of the BJT devices from simulation are chosen as the BJT structures to be tapeouted. The results of actual device structures measurement and electrical analysis show that the BJT device structures which can provide higher current gain and improve the characteristics of amplifying are actually carried out. Furthermore, The simulation software are also utilized to design N channel JFET which have good turn on characteristics, and via actual tapeout, we have successfully integrated N channel JFET into the 0.25um BCD process, which provides IC designer more choices of devices. It is also beneficial to utilize the merits of JFET to improve the performance of the whole circuit.

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