降低消耗功率已經變成了一個日益重要的問題，對於未來的超大型積體電路設計來說。特別是針對一些可攜帶式的產品以及高密度的大型系統。
在這篇論文中，我們審慎地探討一種針對延展是有限狀態機(EFSM)來降低功率消耗的設計技巧。

一般而言，在CMOS的數位電路應用中，大部分的功率消耗市由於電路狀態切換所產生。這個技巧是架構在一般的動態功率消耗管理的概念上，用來減少電路中不必要的狀態切換。如果我們暫時不需要某個小電路的運算結果，但是這個小電路會因為輸入的改變而一直產生狀態切換的動作，

那麼就將這個小電路的輸入資料暫時阻擋起來，不要讓資料進入到電路中造成狀態的切換，如此就可減少一些功率消耗。

當需要這個電路的運算結果時，才讓輸入資料進入到電路中運算。

我們會先去分析延展式有限狀態機，找出所有會產生多餘運算的電路。

這我們分成兩個部分，第一個部分是由延展式有限狀態機(EFSM)的狀態資訊來分析，另一個部分是由延展式有限狀態機的轉換資訊來分析。

然後利用所分析出來的資訊，使用輸入閘控制的方式來減少不必要的狀態變換，來降低功率的消耗。

然後我們在有舉一個例子，並將上面所說的技巧應用上去。

在這個例子中，我們最多可以減少31\%的功率消耗，而面積增加16\%，時間也僅增加2\%。

Low-power has become one of the predominant features in modern VLSI designs, espically for portable devices and high-density systems.
In this thesis, we investigate a low-power design technique for Extended Finite State Machines (EFSM). It is based on the general dynamic power management concept, in which the unnecessary operations in a design are dynamically disabled

to reduce the overall power consumption. The contribution of this thesis is mainly a systematic procedure to identify almost maximum amount of unnecessary operations in a design represented

as an EFSM. There are two levels of unncessary operations to be exploited - one is based on machine state information, while the other is based on the state transition information. After

the extraction of these unnecessary operations, an input-gating based low-power architecture is used to synthesize the final circuit. We tested this technique on a design computing a number's montgomery inverse. Experimental results show that 31% power reduction can be achieved at the costs of only 2% timing penalty and 16% area overhead.

S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits Analysis and Design.The
McGraw-Hill Companies, Inc., 2 ed., 1999.
R. H. Katz, Contemporary Logic Design. The Benjamin/Cummings Publishing Company, Inc.,
1994.