打線結合是目前在系統封裝設計裡連接不同晶片之間的訊號最流行的方法之一。腳位指定在實體設計裡是一個很重要的問題，因為腳位指定的結果會引響系統封裝設計的製程花費和最後的成品效率。在這篇論文裡，我們探討腳位指定的問題，我們問題的目標是要去把所有的訊號線都指定到晶片上面的腳位，並且不能有非法的訊號線橫跨產生，最後還要去使所有指定到晶片上面的訊號線加起來的連線長度越短越好。我們一開始會先考慮特別的測試例子，並且提出了最小成本大流量的方法可以在多項式時間內找到最佳解。接著我們提出第二的方法，第二方法包含兩的部分，第一個部分是的修改的左緣演算法的方法，第二個部分是整數線性規劃的方法，第二個方法可以用在任何所有的測試例子上。最後的實驗結果也顯示出我們方法很有效率且也很有引響力。根據我們現有的資訊，我們的研究是第一個探討腳位指定的問題並且提出了幾個很有前景方法。

Wire bonding is the most popular method to connect signals between dies in System-
in-Package (SiP) design nowadays. Pad assignment, which assigns inter-die signals to
die pads so as to facilitate wire bonding, is an important physical design problem for
SiP design because the quality of a pad assignment solution aects both the cost and
performance of a SiP design. In this thesis, we study a pad assignment problem, which
prohibits the generation of illegal crossings and aims to minimize the total signal wire-
length, for die-stacking SiP design. We rst consider a variety of special cases and present
a minimum-cost maximum-
ow based approach to optimally solve them in polynomial
time. We then describe an approach, which uses a modied left edge algorithm and an
integer linear programming technique, to solve the general case. Encouraging experimen-
tal results are shown to support our approaches. To the best of our knowledge, our work
is the rst one which addresses a pad assignment problem for die-stacking SiP design and
gives promising solutions.

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[8] R. J. Vanderbei, Linear Programming: Foundations and Extensions. Springer, 2007.

[9] CPLEX. [Online]. Available: http://www.ilog.com

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