Clock skew minimization has been an important design constraint. However, due to the complexity of Process, Voltage, and Temperature (PVT) variations, the minimization of clock skew has faced a great challenge. To overcome the influence of PVT variations, several previous works proposed Post Silicon Tuning (PST) architecture to dynamically balance the skew of a clock tree. In the PST architecture, there are two main components: Adjustable Delay Buffer (ADB) and Phase Detector (PD). Most previous works focus on determining good positions of ADBs in a PST design. In this paper, we first show that which pairs of FFs are connected to PDs, called PD structure, also greatly influence the complexity of hardware control for a PST design. Without careful planning of a PD structure, we need large number of control signals to adjust the delays of ADBs. In addition, we also show that a PD structure may influence the accuracy of the clock skew. Among possible connection structures, this work proposes an efficient PD structure which not only simplifies the hardware control but also minimizes the clock skew of a PST design.

時脈偏移最小化已經成為電路設計中重要的條件限制，然而，因為製程、電壓、溫度的變異度越來越嚴重，使得時脈偏移最小化面臨很大的挑戰。為了克服製程、溫度、電壓變異的影響，有許多研究提出了後製階段時脈偏移的架構來動態的平衡時鐘數的時脈偏移。在此種架構下，最主要的兩種元件分別為可調變延遲緩衝器和相位偵測器；大部份的研究都專注在可調變延遲緩衝器的位置擺放問題。本篇論文首先對於由許多相位偵測器連接而成的架構來進行分析，並且分析此架構對於硬體控制的複雜度有很大的關係。如果沒有建立好的相位偵測架構，就需要許多控制訊號來調整可調變延遲緩衝器。此外我們也分析相位偵測架構對於時脈偏移的影響會使得相位偵測器測出不準確的時脈偏移。在眾多的連接方式中，我們提出了一種有效率的相位偵測架構不只簡化硬體控制的複雜度而且也減緩了整體的相位偏移。

[1] Charles E. Dike, Nasser A. Kurd, Priyadarsan Patra, and Javed Barkatullah, "A design for digital, dynamic clock deskew," Digest of technical papers of the symposium on VLSI circuits, 2003.
[2] Charles J. Alpert, Anirudh Devgan, and Stephen T. Quay, "Buffer insertion with accurate gate and interconnect delay computation," Proceedings of the 36th ACM/IEEE conference on Design automation, 1999.
[3] Eiichi Takahashi, Yuji Kasai, Masahiro Murakawa, and Tetsuya Higuchi, "A post-silicon clock timing adjustment using genetic algorithms," Digest of technical papers of the symposium on VLSI circuits, 2003.
[4] George Geannopoulos, and Ximing Dai "An Adaptive Digital Deskewing Circuit for Clock Distribution Networks, "Digest of Technical Papers of IEEE International Solid-State Circuits Conference, 1998.
[5] Jason Cong, Zhigang Pan, Lei He, Cheng-Kok Koh, and Kei-Yong Khoo, "Interconnect design for deep submicron ICs," Proceedings of the IEEE/ACM international conference on Computer-aided design, 1997.
[6] Jeng-Liang Tsai, and Lizheng Zhang and Charlie Chung-Ping Chen, "Statistical timing analysis driven post-silicon-tunable clock-tree synthesis," Proceedings of the IEEE/ACM International conference on Computer-aided design, 2005.
[7] John F. Ewen, Albert X. Widmer, Mehmet Soyuer, Kevin R. Wrenner, Ben Parker, and Herschel A. Ainspan, "Single-Chip 1062Mbaud CMOS Transceiver for Serial Data Communication," Proceedings of the IEEE International Solid-State Circuits Conference, 1995.
[8] K. Bernstein , D. J. Frank, A. E. Gattiker, W. Haensch , B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson,N. J. Rohrer, "High-performance CMOS variability in the 65-nm regime and beyond," IBM Journal of Research and Development, v.50 n.4/5, p.433-449, 2006.
[9] Mac Y.C. Kao, H.M. Chou, K.T. Tsai, and S.C. Chang, "Synthesis of an Efficient Controlling Structure for Post-Silicon Clock Skew Minimization," Proc. of International Conference on Computer Aided Design, ICCAD, pp. 746-749, 2010.
[10] Nasser A. Kurd, Javed S. Barkatullah, Rommel O. Dizon, Thomas D. Fletcher, and Paul D. Madland, "A Multigigahertz Clocking Scheme for the Pentium 4 Microprocessor," IEEE Journal of Solid State Circuits, vol. 36, 2001.
[11] Patrick Mahoney, Eric Fetzer, Bruce Doyle, Sam Naffziger, "Clock Distribution on a Dual-Core, Multi-Threaded Itanium-Family Processor," Proceedings of the IEEE International Solid-State Circuits Conference, 2005.
[12] Simon Tam, Rahul Dilip Limaye, and Utpal Nagarji Desai, "Clock Generation and Distribution for the 130-nm ItaniumR 2 Processor with 6-MB On-Die L3 Cache," IEEE Journal of Solid State Circuits, vol. 39, 2004.
[13] Simon Tam, Stefan Rusu, Utpal Nagarji Desai, Robert Kim, Ji Zhang, and Ian Young, "Clock generation and distribution for the first IA-64 microprocessor," IEEE Journal of Solid State Circuits, vol. 35, 2000.
[14] Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho, Kenneth D. Boese, Student Member, ZEEE, and Andrew B. Kahng, "Zero Skew Clock Routing with Minimum Wirelength," IEEE Transaction on Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, 1992.
[15] Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho, "Zero skew clock net routing," Proceedings of the 29th ACM/IEEE conference on Design automation, 1992.
[16] Uday Padmanabhan, Janet Meiling Wang, Senior Member, IEEE, and Jiang Hu, "Robust Clock Tree Routing in the Presence of Process Variations," IEEE Transaction on Computer-aided Design of Integrated Circuits and Systems, VOL. 27, NO. 8, 2008.
[17] Vishal Khandelwal and Ankur Srivastava, "Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation," IEEE Transaction on Computer-aided Design of Integrated Circuits and Systems, VOL. 27, NO. 4, 2008.
[18] Yi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, Jiarong Tong, Wei Cai, and Jia Ni, "Timing Yield Driven Clock Skew Scheduling Considering non-Gaussian Distributions of Critical Path Delays," Proceedings of the 45th ACM/IEEE conference on Design automation, 2008.
[19] Y.C. Kao, H.M. Chou, K.T. Tsai, and S.C. Chang, ”An Efficient Phase Detector Connection Structure for the Skew Synchronization System,” Proceedings of Design Automation Conference, DAC, pp. 729-734, 2010.
[20] Yu-Shih Su,Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang, "Value assignment of adjustable delay duffers for clock skew minimization in Multi-Voltage Mode Designs," Proceedings of the IEEE/ACM International conference on Computer-aided design, 2009.