使用Quiet-Bitline架構所設計的低功率靜態隨機存取記憶體

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研究生：	鄭世保 Shin-Pao Cheng
論文名稱：	使用Quiet-Bitline架構所設計的低功率靜態隨機存取記憶體 A Low-Power SRAM Design Using Quiet-Bitline Architecture
指導教授：	黃錫瑜 Shi-Yu Huang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	50
中文關鍵詞：	SRAM 、Quiet-Bitline 、Latch type 、Dynamic decoder 、Pulse wordline 、Static noise margin
相關次數：	點閱：2 下載：0
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本篇論文在於使用Quiet-Bitline的架構來設計一個低功率的靜態隨機存取記憶。其包含了兩個主要的技術：第一，在做寫入動作時，我們使用單邊驅動，單邊處於浮接的方法，來減少多餘的電荷被注入到位元線上。並加上使用pulse wordline 的方式，來減少wordline 打開的時間以減少功率消耗。第二，在做讀取動作時，傳統SRAM會先使用預先充電電晶體將位元線充電到VDD，但我們使用關閉預先充電電晶體的方法，其目的在於讓全部的位元線能儘可能的維持在低電壓的情況，如此，可節省對位元線充電所消耗的功率。但將位元線的電壓準位維持在低電壓的話，可能會有static noise margin(SNM)的問題。因此，我們的規格是訂在SNM=0.3V 左右。用HSPICE 來模擬1K-bit Quiet-Bitline 靜態隨機存取記憶的功率消耗的結果，可發現其功率消耗可比傳統靜態隨機存取記憶體節省約76%左右。但付出的代價是, 其Access time會比傳統靜態隨機存取記憶體稍慢一些。本晶片有經由國家晶片設計中心(CIC)下線到台積電。並使用台積電 0.18um 1P6M 製程。由量測儀器所量到的數據和模擬頗為類似，足可證明Quiet-Bitline SRAM 確實可達到low power 的效果，並且能夠正常的動作。

This thesis presents a low-power SRAM design with Quiet-Bitline architecture by incorporating two major techniques. Firstly, we use a one-side driving scheme for the write operation to prevent the excessive full-swing charging on the bitlines. Secondly, we use a precharge-free pulling scheme for the read operation so as to keep all bitlines at low voltages at all times. HSPICE simulation on a 1K-bit SRAM macro shows that such architecture can lead to a significant 76% power reduction over a self-designed baseline low-power SRAM macro.

Contents
Abstract………………………………………………………………01
Contents………………………………………………………………04
List of Figures……………………………………………………06
List of Tables………………………………………………………08
Chapter 1 Introduction……………………………………………09
1.1 Motivation………………………………………………………09
1.2 Idea of our Quiet-Bitline SRAM……………………………10
1.3 Thesis organization…………………………………………11
Chapter 2 The concept of conventional SRAM…………………12
2.1 Basic column structure………………………………………12
2.2 The 6-T SRAM cell……………………………………………13
2.3 Basic read operation of conventional SRAM……………14
2.4 Basic write operation of conventional SRAM……………17
2.5 The strategies of reduce power consumption in conventional SRAM…………………………………………………19
2.6 Divided wordline technique…………………………………20
2.7 Pulsed wordline technique…………………………………21
Chapter 3 A 1K-bit Quiet-Bitline SRAM circuit design……23
3.1 Introduction……………………………………………………23
3.2 Overall strategy………………………………………………24
3.3 Read operation of Quiet-Bitline SRAM……………………25
3.4 Write operation of Quiet-Bitline SRAM…………………28
3.5 Worst–Case scenarios………………………………………30
3.6 Dynamic decoder………………………………………………31
3.7 Latch-type sense amplifier…………………………………33
3.8 Analysis of static noise margin…………………………35
Chapter 4 Implementation and experiment results…………37
4.1 The features in this SRAM…………………………………37
4.2 The implementation of 1K-bit Quiet-Bitline SRAM……38
4.3 The experiment results of 1K-bit Quiet-Bitline SRAM…40
Chapter 5 Conclusion………………………………………………46
Reference……………………………………………………………47

List of Figures
Fig.2-1: One column circuit of SRAM……………………………12
Fig.2-2: The 6-T SRAM cell………………………………………14
Fig.2-3: Bitline discharging for the read operation………16
Fig.2-4: The relative waveforms for the bitline discharge………………………………………………………………17
Fig.2-5: Bitline charging and discharging for the write operation………………………………………………………………19
Fig.2-6: Key signal waveforms of write operation…………19
Fig.2-7: Divided wordline structure……………………………21
Fig.2-8: Pulse wordline circuit…………………………………22
Fig.2-9: A pulse wordline generator and its output………22
Fig.3-1: The block diagram of 1K-bit Quiet-Bitline SRAM…23
Fig.3-2: The read circuit of Quiet-Bitline SRAM……………………………………………………………………27
Fig.3-3: Quiet-Bitline SRAM read operation waveforms……27
Fig.3-4: Quiet-Bitline SRAM write architecture and waveforms………………………………………………………………29
Fig.3-5: Effects of 15 consecutive write ‘1’ operations on bitline……………………………………………………………31
Fig.3-6: The schematic of dynamic decoder……………………32
Fig.3-7: The waveforms of dynamic decoder……………………33
Fig.3-8: The schematic of latch type sense amplifier……34
Fig.3-9: The waveforms of latch type sense amplifier………………………………………………………………35
Fig.3-10: Illustration of static noise model………………36
Fig.3-11: SNR of an SRAM cell……………………………………36
Fig.4-1: The layout of 1K-bit SRAM……………………………38
Fig.4-2: The die photo of chip…………………………………39
Fig.4-3: The simulation waveforms of 1K-bit Quiet-Bitline SRAM……………………………………………………………………41
Fig.4-4: The waveforms in CIC tester…………………………42
Fig.4-5: The simulation waveforms with -20% VDD……………43
Fig.4-6: Data output in differential corner test…………44

List of Tables
Table.3-1: Logic table of write operation……………………30
Table.4-1: Characteristic table…………………………………39
Table.4-2: Pin function of 1K-bit Quiet-Bitline SRAM……40
Table.4-3: Comparisons of conventional SRAM and Quiet-bitline SRAM…………………………………………………………45
Table.4-4: Comparisons of real chip and simulation results …………………………………………………………………………45

                                

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