一個可在單週期執行雙濾波功能的去區塊雜訊濾波器架構應用在QFHD H.264/AVC解碼器

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研究生：	林元淳 Yuan-Chun Lin
論文名稱：	一個可在單週期執行雙濾波功能的去區塊雜訊濾波器架構應用在QFHD H.264/AVC解碼器 A Two-Result-Per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder
指導教授：	林永隆 Youn-Long Lin
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	40
中文關鍵詞：	視訊壓縮、去區塊、濾波器、高畫質
外文關鍵詞：	video, deblocking filter, H.264, QFHD
相關次數：	點閱：3 下載：0
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我們提出H.264/AVC解碼中去區塊雜訊濾波器的高效能全硬體架構設計。基於QFHD (4X FULL 1080HD) 解碼器嚴苛的高效能需求，我們的架構分別在處理週期，晶片外部記憶體存取，以及運作時脈三方面同時進行效能的最佳化，針對處理週期，我們達到近於理論最佳值的執行週期。針對外部記憶體存取考量，我們在內部記憶體與外部記憶體存取之間取得最佳平衡，使得我們架構能以少量的內部記憶體便能省下大部分的不必要的外部記憶體資料量。針對運作時脈，我們以五級管線架構來實現我們的邊緣濾波器，使得此架構更能夠進一步提升運作頻率滿足高頻高效能的視訊應用。此創新架構成功地利用演算法的彈性，使我們的邊緣濾波器可在單週期執行雙濾波功能，其中，我們提出的邊緣濾波器具有提前遞送的機制來避免管線延遲以及減少像素轉向暫存器的數量。另一方面，我們的架構可依照區塊雜訊在邊界強度的分佈情形來動態調整電路模式，因此在處理P 或是B 的視訊畫面時，此架構可更進一步利用快速略過模式來縮短執行週期以及減少外部記憶體存取。除此之外，我們還利用硬體共享的方式使我們能以有效的晶片面積實現此超高效能架構。根據這些創新，我們提出的架構能滿足超高效能以及低功耗的視訊應用，並僅以195 MHZ的時脈支援QFHD每秒60張畫面的即時解碼。

We propose a high-performance hardwired Deblocking Filter (DF) for H.264/AVC video decoding. To fulfill the demand of ultra high throughput for QFHD (4x Full 1080HD), we optimize processing cycle, external memory access and working frequency of our architecture. Our Two-Result-Per-Cycle edge filter achieves near optimal processing cycle. It takes only 48 clock cycles to filter a macroblock in best case and 100 in worst case. Furthermore, it can save most unnecessary off-chip memory traffic with efficient on-chip memory. Our circuit supports skip mode to further reduce processing cycles and off-chip memory access in inter-predicted frame. Also it employs a 5-stage pipelined, and hardware-shared dual-edge-filter to generate two filtering results every cycle. Running at 195 MHz, it can support QFHD @ 60fps application.

Contents
Abstract    I
Contents    II
List of Figures    III
List of Tables    IV
Chapter 1    1
Introduction    1
Chapter 2    4
Deblocking Filter Algorithm    4
2.1    Filtering Order    5
2.2    Boundary Strength and Thresholds    7
2.3    Edge Filter    9
Chapter 3    11
Design Considerations and Related Work    11
3.1    Processing Cycles    11
3.2    External Memory Traffic    13
3.3    Working Frequency    14
3.4    Hardware Cost    15
Chapter 4    17
Proposed Design    17
4.1    Filtering Mode Analysis    17
4.2    Proposed Filtering Order    18
4.3    Proposed Deblocking Filter    19
4.4    Memory Organization    21
4.5    Two-Result-Per-Cycle Edge Filter    22
4.6    Filtering Cycle Analysis    25
Chapter 5    28
Experimental Results    28
5.1    Implementation Results    28
5.2    Comparisons    31
Chapter 6    37
Conclusion    37
Bibliography    38

List of Figures

Figure 1 A QFHD H.264/AVC Decoder Employs Proposed DF    2
Figure 2 Inputs and Outputs of Deblocking Filter    4
Figure 3 Involved Pixels for Deblocking One Macroblock    6
Figure 4 Horizontal and Vertical Filtering of (a) Luma and (b) Chroma Blocks    7
Figure 5 Edge Filter Flow Chart    9
Figure 6 Strong Filter (BS=4) Flow Chart    10
Figure 7 Weak Filter (BS=3) Flow Chart    10
Figure 8 Processing Cycles Analysis of Different Decoding Stages    12
Figure 9 Average External Memory Traffic of Different Modules for One MB    14
Figure 10 Profiling of Skip-top Mode & Skip-all Mode in P-type Frames    18
Figure 11 Proposed Filter Order    19
Figure 12 Proposed Deblocking Filter Block Diagram    20
Figure 13 Different Memory Organizations of One MB    22
Figure 14 Proposed Pipelined Two-Result-Per-Cycle Edge Filter    23
Figure 15 Pipeline Hazard Illustration    24
Figure 16 Pipeline Forwarding for Filtering Step 9-10    25
Figure 17 Filtering Timing of One MB    26
Figure 18 Non-skip-all Mode Timing Diagram    27
Figure 19 Average Processing Cycle Count Per MB    30
Figure 20 Average External Traffic for Upper Neighboring Pixels Per MB    31
Figure 21 Cycle Comparison with Previous Works    32
Figure 22 Comparison of External Traffic Per MB vs. Local SRAM Size for QFHD Decoder    33




List of Tables

Table 1 Condition for Determining Boundary Strength    8
Table 2 Code Coverage of Verification Navigator    28
Table 3 Gate Count of Proposed Design    29
Table 4 Comparison with Previous Designs 1    34
Table 5 Comparison with Previous Designs 2    35
Table 6 Comparison with Previous Designs 3    36

                                

Bibliography
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