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研究生: 郭皇志
論文名稱: 針對幅內編碼的演算法與硬體架構設計
Algorithm and Hardware Architecture Design for Intra-frame Encoding
指導教授: 林永隆
口試委員: 王家祥
黃稚存
郭峻因
張添烜
林嘉文
學位類別: 博士
Doctor
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2013
畢業學年度: 101
語文別: 英文
論文頁數: 97
中文關鍵詞: 幅內編碼演算法
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  • 幅內編碼已被廣泛地應用在許多的影像產品中,包括了監視系統,數位電影,和視訊會議等。這些產品採用幅內編碼的原因有二。其一,幅內編碼能對每張幅提供隨機存取的功能,使得影像編輯與後製變得容易。其二,幅內編碼演算法的複雜度較低,相對的所需要的硬體資源也就較少。

    在此論文的第一部分,我們針對影像顯示幅提出了一個低複雜度的幅內編碼演算法。我們的演算法中整合了字典編碼,霍夫曼(Huffman)編碼,和三個創新的編碼方法來達到高壓縮率。我們定量地分析影像顯示幅的特性來設計演算法。首先我們提出一個二階段分類法(Two-level classification)來將所有的像素分為三類,接著我們使用字典編碼和新提出的自適應字首位元截斷法(Adaptive prefix bit truncation)來產生每個的像素的碼字(codeword),並使用霍夫曼編碼來算出每個碼字的值。我們也提出了一個碼字首位元壓縮法(Head code compression)來進一步壓縮碼字。實驗結果顯示我們所提出的演算法比起過去的方法高至少百分之十的壓縮率。此外我們也將所提出的演算法整合至一個H.264/AVC的解碼器中,模擬結果顯示在存取影像顯示幅時,我們的演算法能夠減少約百分之五十九的時間。

    H.264/AVC,目前最被廣泛使用的影像編碼標準,也制定了新的幅內編碼工具
    來達到高壓縮效能,但這些工具也使得H.264/AVC的運算複雜度大為提高。在此論文的第二部分,我們提出了一個高效率的H.264/AVC幅內編碼器。在我們的編碼器硬體架構中,我們提出了數個創新的方法來解決幅內編碼中,因4×4亮度(luma)區塊(block)間的資料相依性而造成的效能瓶頸。我們也整合了一個高效能的全文自適應二進制算數編碼器(CABAC),並且採用時脈控制技術(clock-gating)來降低編碼器功耗。使用130奈米的CMOS製程合成電路,在時脈為108MHz下,我們的編碼器一共使用了約十九萬個邏輯閘及花費19.8毫瓦的功來壓縮每秒三十幅的1080p影像,壓縮後的影片也能維持跟使用軟體處理一樣好的影像品質。實驗結果顯示,我們的幅內編碼器比起現行的其他編碼器更有效率。


    Abstract i Contents iii List of Tables vi List of Figures viii 1 Introduction 1 2 A Low-Complexity Lossless Intra-frame Compression Algorithm for Display Frames 4 2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Related Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2.1 Block-based Lossless Compression Algorithms . . . . . . . . . 7 2.2.2 Line-based Lossless Compression Algorithms . . . . . . . . . . 9 2.2.3 Summary of Previous Works . . . . . . . . . . . . . . . . . . . 11 2.3 Proposed Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.2 Two-level Classification Scheme . . . . . . . . . . . . . . . . . 16 2.3.3 Adaptive Prefix Bit Truncation Scheme . . . . . . . . . . . . . 19 2.3.4 Codeword Bits Assignment . . . . . . . . . . . . . . . . . . . . 22 2.3.5 Head Code Compression Scheme . . . . . . . . . . . . . . . . 24 2.3.6 An Illustrative Example . . . . . . . . . . . . . . . . . . . . . 26 2.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3 An Efficient Hardware Architecture for H.264/AVC Intra-frame En- coding 36 3.1 H.264/AVC Intra-frame Encoding . . . . . . . . . . . . . . . . . . . . 36 3.2 Design Challenge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3 Related Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3.1 Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3.2 Design Targets . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.4 Proposed Performance Enhancement Approaches . . . . . . . . . . . 51 3.4.1 Hardware Utilization Optimized Schedule . . . . . . . . . . . . 51 3.4.2 Resource Sharing Among Skew Modes . . . . . . . . . . . . . 53 3.4.3 Referenced Column First Reconstruction . . . . . . . . . . . . 55 3.5 Proposed Architecture and System . . . . . . . . . . . . . . . . . . . 57 3.5.1 Pipeline Schedule . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.5.2 AMBA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . 60 3.5.3 Encoder Core Implementation . . . . . . . . . . . . . . . . . . 62 3.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4 Conclusion and Future Work 76 Bibliography 79

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