在本論文中，我們研究考量多重微影技術放置的合法化問題，並考慮到整數倍列高標準元與多重微影層。進行時序優化所使用之緩衝閘插入與標準元件大小之更改等技術極有可能導致標準元件之間重疊且無法進行多重微影分解，因而此問題將針對已知佈局分解的合法標準元件擺置進行時序優化後的情況進行處理。我們提出了一個方法以解決上述之標準元件放置合法化之相關問題，利用合法的擺置標準元件並且令每個多重微影層產生盡可能少的著色衝突來處理此問題。實驗結果顯示，我們提出的研究方法可以同時使給定的佈局合法化並為每個多重微影層找到高品質的多重微影佈局分解。在每個實驗測資都花費合理的運行時間，且線長僅增加微小的數量。

In this thesis, we study a multiple-layer multiple-patterning aware placement legalization problem for designs with multiple-row height standard cells. Such a problem is necessary to be addressed especially when performing timing optimization on a legal placement with a known layout decomposition for each multiple-patterning layer, because the inserted buffers and resized cells may cause cell overlapping and their layout is not decomposed yet for each multiple-patterning layer.
We propose a methodology to solve the addressed placement legalization problem by making the placement become legal and each multiple-patterning layer has as few coloring conflicts as possible.
Experimental results show that our methodology can simultaneously legalize the given placement and find a high-quality layout decomposition for each multiple-patterning layer with reasonable run time for each test case while the wirelength only increases a very small amount.

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