低功率標準元件庫研發｜國立清華大學博碩士論文庫

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研究生：	侯芪焜 Chi-Kuen Ho
論文名稱：	低功率標準元件庫研發 A Low Power Standard Cell Library Development
指導教授：	馬席彬 Hsi-Pin Ma
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	94
語文別：	英文
論文頁數：	146
中文關鍵詞：	電源供應電壓、臨限電壓、次臨限電流、功率消耗、多重臨限電壓互補式金氧半場效電晶體、標準元件庫、疊接
外文關鍵詞：	power supply voltage, threshold voltage, sub-threshold current, power consumption, multi-threshold CMOS, standard cell library, stack
相關次數：	點閱：2 下載：0
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縮小面積、降低電源供應電壓(power supply voltage)以及減小電晶體的臨限電壓(threshold voltage)是製程技術演進上的趨勢，然而，它同時也令次臨限電流(sub-threshold current)在總體功率消耗(power consumption)上的比例大大的提高。多重臨限電壓互補式金氧半場效電晶體(multi-threshold CMOS)是近年來越來越受重視的一種低功率技術，它能夠有效的減少低臨限電壓所帶來的次臨限電流，並且保有電路原有的效能。
　　在本論文裡，我將MTCMOS技術完整的應用到標準元件庫(standard cell library)的設計中，並且引入了疊接(stack)電晶體的概念來強化MTCMOS其改善次臨限電流的能力。標準元件庫在數位電路設計的領域中極其重要，它普遍被應用在Cell-Based Design中，電路設計者能夠藉由Cell-Based Design Flow，快速的利用元件庫中的元件來完成他們的設計，因此，元件庫的特性的優劣會直接的影響到電路性能的好壞。我以MTCMOS技術分別針對TSMC 0.18μm以及UMC 0.18μm兩種製程設計了兩套標準元件庫，並實際以Cell-Based Design Flow實現了兩組測試電路，經過模擬的驗證，都顯示出其我所提出的標準元件庫能有效的降低功率的消耗，特別是對於改善次臨限電流，更是成效卓著。

Scaling down, power reduction and reducing threshold voltage of transistors are the future trends of process development. However, it also causes sub-threshold leakage current to become an increasingly large component of total power dissipation. Recently, multi-threshold voltage CMOS technology already has attracted more and more attention for its low power capacity. The technology can reduce efficiently the sub-threshold leakage current which low threshold voltage results in. Besides, it still can retain the original circuit performance without too large overhead.
In this thesis, I apply MTCMOS technology to standard cell library design, besides, I inject stack transistors concept to enforce MTCMOS capacity of reducing sub-threshold leakage current. Standard cell library plays a really important role in digital circuit design; it is utilized universally for Cell-Based Design. A circuit designer can quickly use these elements of standard cell library to realize their design through Cell-Based Design flow. Therefore, the good or bad of cell library will directly affect the feature of designed circuits. Based on MTCMOS technology, I proposed two sets of standard cell libraries what they are used for TSMC 0.18μm and UMC 0.18μm process separately. By Cell-Based Design flow, I implemented two different test circuits with them. And through SPICE simulation, the results both proved that our standard cell libraries can lower efficiently power dissipation, especially for the improvement of sub-threshold leakage current.

Introduction and Background                              1
1 Introduction……………………………………………………………………1
2 Static Leakage Current………………………………………………………...3
2.1 Leakage Current Categories……………………………………………..3
2.2 Sub-threshold Leakage…………………………………………………..5
3 Multi-threshold CMOS Technology…………………………………………...7
3.1 Principle…………………………………………………………………7
3.2 Improvement…………………………………………………………….9
4 Organization of Thesis……………….…….…………………………………11

CMOS Leakage Characterization                          13
1 Leakage models………………………………………………………………13
2 Sub-threshold Current versus Threshold Voltage…………………………….14
3 Sub-threshold Current versus Temperature……….…………………………15
4 VGS and VDS Affection…….….…………………………….……………….16
5 Device Size Affection…..…..………………………………………………17

MTCMOS Standard Cell Library Development              21
1 Standard Cell Library Development………………………………………..21
1.1 Design Flow…………………………………………………………..21
1.2 Contents in the Standard Cell Library…………………………………22
2 Cell Characterization and Model Establishment……………………………25
2.1 Introduction of Cell Characteristics Extraction and Model
 Establishment Flow……………………………………………………25
2.2 Kinds of Characteristics and Extraction Theorem……………………..26
3 Concept of MTCMOS Standard Cell Library……………………………….27
4 Specification and Description of Standard Cell Library…………………….29
4.1 UMC 0.18μm Process………………………………………………….29
4.2 TSMC 0.18μm Process…………………………………………………30
5 Standard Cell Library Design Rules………………………………………….31
6 Sequential Circuits of MTCMOS…………………………………………….35
6.1 Design of Sequential Circuits…………………………………………..35
6.2 D Flip-Flop Circuit for MTCMOS Standard Cell Library……………..34

Cell-Based Design Preparation                            41
1 Cell-Based Design Flow…….………………………………………………41
2 Synthesis……………………………………………………………………..43
2.1 Compiling Library……..……………………………………………….43
2.2 Modifying Verilog Code………………………………………………44
3 Automatic Placement and Routing…………………………………………..48

Test Circuit                                             51
1 TSMC 0.18μm Process……………………………………………………….51
1.1 Introduction to Test Circuit…………………………………………….51
1.2 Architecture Design…………………………………………………….52
1.3 Implementation of Test Circuit…………………………………………53
           5.1.3.1 Floorplan………………………………………………………53
           5.1.3.2 Design Testability….…..………………………………………55
           5.1.3.3 Simulation Results……………………………………………56
2 UMC 0.18μm Process………………………………………………………58
2.1 Introduction to Test Circuit………………….…………………………58
2.2 Architecture Design…………………………………………………….58
2.3 Implementation of Test Circuit…………………………………………62
           5.2.3.1 Floorplan………………………………………………………62
           5.2.3.2 Simulation Results…….………………………………………63

Future Works and Conclusions                            67
1 Future Works …...……………………………………………………………67
2 Conclusions…………………………………………………………………68

Appendix A: Cell Library Information-TSMC 0.18μm 1P6M Process
Appendix B: Cell Library Information-UMC 0.18μm 1P6M Process

                                

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