研究生: |
林宗達 Lin, Tsung-Da |
---|---|
論文名稱: |
高效能自對準反轉通道砷化銦鎵金氧半場效電晶體 High Performance Self-aligned Inversion-channel InGaAs MOSFETs |
指導教授: |
洪銘輝
Hong, Minghwei 郭瑞年 Kwo, Raynien |
口試委員: | |
學位類別: |
博士 Doctor |
系所名稱: |
工學院 - 材料科學工程學系 Materials Science and Engineering |
論文出版年: | 2010 |
畢業學年度: | 99 |
語文別: | 英文 |
論文頁數: | 111 |
中文關鍵詞: | 高介電常數氧化物 、氧化鎵 、氧化釓 、砷化銦鎵 、金氧半場效電晶體 、分子束磊晶 |
外文關鍵詞: | high-k dielectrics, Ga2O3, Gd2O3, InGaAs, MOSFETs, Molecular Beam Epitaxy |
相關次數: | 點閱:1 下載:0 |
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High κ gate dielectrics on channel materials with high carrier mobility are urgently demanded for achieving high performance and low power complementary metal-oxide-semiconductor (CMOS) technologies beyond the 15 nm node. This work is carried out not only to realize high performance III-V MOSFETs but also to project the ultimate performance of III-V MOSFETs. Ultra-high-vacuum (UHV) deposited Al2O3/Ga2O3(Gd2O3) [GGO] on InGaAs have exhibited low interfacial densities of states of ~ 10^11 eV^(-1)•cm^(-2), small capacitance equivalent thickness of ~1 nm, thermal stability at high temperatures higher than 850 – 900℃, and controllable metal-work-function dependent flat-band voltages.
In this dissertation, high performance self-aligned inversion-channel InGaAs MOS field-effect-transistors (MOSFETs) have been demonstrated using UHV-deposited Al2O3/GGO dual-layer dielectrics and sputtered TiN metal gates. The 1μm-gate-length Al2O3/GGO/In0.53Ga0.47As MOSFETs have demonstrated record-high maximum drain current of 1.05 mA/μm, peak transconductance of 714 μS/μm, and a high mobility of 1300 cm^2/V•s. In addition, the same transistors exhibits excellent embedded radio-frequency characteristics, including a fT of 17.9 GHz and a fmax of 11.2 GHz. Moreover, In0.75Ga0.25As MOSFETs, also with a gate length of 1 μm, have achieved a maximum drain current of 1.23 mA/μm, a peak transconductance of 464 μS/μm and a peak field-effect electron mobility of 1600 cm^2/V•s. The Al2O3/GGO/InGaAs MOSFETs have set records, not only for III-V MOSFETs but also for all enhancement-mode MOSFETs with similar gate-lengths, regardless of channel materials and device configurations. They serve the key in realizing ultimately scaled planar device with high performance.
[1] J. Bardeen and W. H. Brattain, "The transistor, a semi-conductor triode," Physical Review, vol. 74 pp. 230-231, 1948.
[2] D. Kahng, "Electric field controlled semiconductor device," U. S. Patent No. 3,102,230, August 27, 1963.
[3] C. J. Frosch and L. Derick, "Surface Protection and Selective Masking during Diffusion in Silicon," J. Electrochem. Soc., vol. 104, pp. 547-552, 1957.
[4] G. E. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, pp. 114-117, 1965.
[5] Intel. Transcript for "Moore's Law: An Intel Perspective". Available: ftp://download.intel.com/museum/Moores_Law/Video-Transcripts/Excepts_A_Conversation_with_Gordon_Moore.pdf
[6] G. E. Moore, "Progress in digital integrated electronics," in Tech. Dig. - Int. Electron Devices Meet., 1975, pp. 11-13.
[7] R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, and A. R. LeBlanc, "Design of ion-implanted MOSFET's with very small physical dimensions," IEEE J. Solid-State Circuit vol. 9, pp. 256-268, 1974.
[8] International Technology Roadmap for Semiconductors (2009 ed.). Available: http://www.itrs.net/
[9] L. Zuckerman, "I.B.M. to make smaller and faster chips - Second breakthrough in a week has wide uses," in The New York Times, Sep. 22, 1997.
[10] P. C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans, and H. Deligianni, "Damascene copper electroplating for chip interconnections," IBM J. Res. Dev. , vol. 42, pp. 567-574, 1998.
[11] R. D. Goldblatt, B. Agarwala, M. B. Anand, E. P. Barth, G. A. Biery, Z. G. Chen, S. Cohen, J. B. Connolly, A. Cowley, T. Dalton, et al., "A high performance 0.13 μm copper BEOL technology with low-k dielectric," in Proc. IEEE Int. Interconnect. Tech. Conf., 2000, pp. 261-263.
[12] K. Maex, M. R. Baklanov, D. Shamiryan, F. Iacopi, S. H. Brongersma, and Z. S. Yanovitskaya, "Low dielectric constant materials for microelectronics," J. Appl. Phys., vol. 93, pp. 8793-8841, 2003.
[13] B. J. FEDER, "I.B.M. stretches silicon in new ways to speed up chips," in The New York Times, Jun. 8, 2001.
[14] IBM. IBM's strained silicon breakthrough image page. Available: http://www.research.ibm.com/resources/press/strainedsilicon/
[15] S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Y. Ma, B. McIntyre, et al., "A logic nanotechnology featuring strained-silicon," IEEE Electron Device Lett., vol. 25, pp. 191-193, 2004.
[16] R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, "High-κ/metal-gate stack and its MOSFET characteristics," IEEE Electron Device Lett., vol. 25, pp. 408-410, 2004.
[17] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, et al., "A 45nm logic technology with high-κ plus metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging," in Tech. Dig. - Int. Electron Devices Meet., 2007, pp. 247-250.
[18] M. Bohr, "The new era of scaling in an SoC world," presented at the IEEE Int. Solid-State Circuits Conf. (ISSCC), 2009.
[19] J. del Alamo and D. Antoniadis, "Emerging nanotechnology and nano- electronics," presented at the IEDM Short Course, 2007.
[20] M. Heyns and W. Tsai, "Ultimate scaling of CMOS logic devices with Ge and III-V materials," MRS Bull., vol. 34, pp. 485-492, 2009.
[21] B. Baker, "Keynote: Silicon leadership—delivering innovation," presented at the Intel Developer Forum (IDF), 2009.
[22] J. Markoff, "For chip makers, hybrids may be a way forward," in The New York Times, Dec. 15, 2008.
[23] D.-H. Kim and J. A. del Alamo, "30 nm E-mode InAs PHEMTs for THz and future logic applications," in Tech. Dig. - Int. Electron Devices Meet., 2008, pp. 719-722.
[24] K. Navrátil, I. Ohlídal, and F. Lukes, "The physical structure of the interface between single-crystal GaAs and its oxide film," Thin Solid Films, vol. 56, pp. 163-171, 1979.
[25] E. I. Chen, J. N. Holonyak, and S. A. Maranowski, "AlxGa1-xAs—GaAs metal—oxide semiconductor field effect transistors formed by lateral water vapor oxidation of AlAs," Appl. Phys. Lett., vol. 66, pp. 2688-2690, 1995.
[26] C. W. Wilmsen, "Chemical composition and formation of thermal and anodic oxide/III-V compound semiconductor interfaces," J. Vac. Sci. Technol., vol. 19, pp. 279-289, 1981.
[27] C. W. Wilmsen, "Physics and chemistry of III-V compound semiconductor interface," C. W. Wilmsen, Ed., New York: Plenum, 1985, p. 435.
[28] H. L. Hartnegal and R. Reimenschneider, "Properties of gallium arsenide," M. R. Brozel and G. E. Stillman, Eds., 3rd ed. London: INSPEC, Institution of Electrical Engineers, 1996, p. 482.
[29] T. Sawada, H. Hasegawa, and H. Ohno, "Electronic properties of a photochemical oxide-GaAs interface," Jpn. J. Appl. Phys., vol. 26, pp. L1871-L1873, Nov 1987.
[30] H. Becke, R. Hall, and J. White, "Gallium arsenide MOS transistors," Solid-State Electron., vol. 8, pp. 813-818, 1965.
[31] S. Tiwari, S. L. Wright, and J. Batey, "Unpinned GaAs MOS capacitors and transistors," IEEE Electron Device Lett., vol. 9, pp. 488-490, 1988.
[32] J. L. Freeouf, D. A. Buchanan, S. L. Wright, T. N. Jackson, and B. Robinson, "Accumulation capacitance for GaAs-SiO2 interfaces with Si interlayers," Appl. Phys. Lett., vol. 57, pp. 1919-1921, 1990.
[33] A. Callegari, P. D. Hoh, D. A. Buchanan, and D. Lacey, "Unpinned gallium oxide/GaAs interface by hydrogen and nitrogen surface plasma treatment," Appl. Phys. Lett., vol. 54, pp. 332-334, 1989.
[34] E. S. Aydil, K. P. Giapis, R. A. Gottscho, V. M. Donnelly, and E. Yoon, "Ammonia plasma passivation of GaAs in downstream microwave and radio-frequency parallel plate plasma reactors," J. Vac. Sci. Technol., vol. 11, pp. 195-205, 1993.
[35] M. Hong, C. T. Liu, H. Reese, and J. Kwo, "Semiconductor-insulator interfaces," in Encyclopedia of Electrical and Electronics Engineering, vol. 19, J. G. Webster, Ed., New York: John Wiley & Sons, 1999, pp. 87-100.
[36] M. Hong, J. Kwo, T. D. Lin, M. L. Huang, W. C. Lee, and P. Chang, "InGaAs, Ge, and GaN Metal-Oxide-Semiconductor Devices with High-k Dielectrics for Science and Technology Beyond Si CMOS," in Fundamentals of III-V Semiconductor MOSFETs, S. Oktyabrsky and P. Ye, Eds., 1st ed: Springer US, 2010, pp. 251-284.
[37] M. Hong, M. Passlack, J. P. Mannaerts, J. Kwo, S. N. G. Chu, N. Moriya, S. Y. Hou, and V. J. Fratello, "Low interface state density oxide-GaAs structures fabricated by in situ molecular beam epitaxy," J. Vac. Sci. Technol. B, vol. 14, pp. 2297-2300, 1996.
[38] M. Hong, J. P. Mannaerts, J. E. Bower, J. Kwo, M. Passlack, W. Y. Hwang, and L. W. Tu, "Novel Ga2O3(Gd2O3) passivation techniques to produce low Dit oxide-GaAs interfaces," J. Cryst. Growth, vol. 175-176, pp. 422-427, 1997.
[39] M. Hong, J. Kwo, A. R. Kortan, J. P. Mannaerts, and A. M. Sergent, "Epitaxial cubic gadolinium oxide as a dielectric for gallium arsenide passivation," Science, vol. 283, pp. 1897-1900, 1999.
[40] J. Kwo, D. W. Murphy, M. Hong, R. L. Opila, J. P. Mannaerts, A. M. Sergent, and R. L. Masaitis, "Passivation of GaAs using (Ga2O3)1 - x(Gd2O3)x, 0 ≤ x ≤1.0 films," Appl. Phys. Lett., vol. 75, pp. 1116-1118, 1999.
[41] J. Kwo, M. Hong, J. P. Mannaerts, Y. D. Wu, Q. Y. Lee, B. Yang, and T. Gustafsson, "Fundamental study and oxide reliability of the MBE grown Ga2-xGdxO3 dielectrics for compound semiconductor MOSFETs," in Mat. Res. Soc. Symp. Proc., 2004, pp. E1.12.1-E1.12.6.
[42] P. D. Ye, G. D. Wilk, B. Yang, J. Kwo, H.-J. L. Gossmann, M. Hong, K. K. Ng, and J. Bude, "Depletion-mode InGaAs metal-oxide-semiconductor field-effect transistor with oxide gate dielectric grown by atomic-layer deposition," Appl. Phys. Lett., vol. 84, pp. 434-436, 2004.
[43] M. M. Frank, G. D. Wilk, D. Starodub, T. Gustafsson, E. Garfunkel, Y. J. Chabal, J. Grazul, and D. A. Muller, "HfO2 and Al2O3 gate dielectrics on GaAs grown by atomic layer deposition," Appl. Phys. Lett., vol. 86, p. 152904, 2005.
[44] M. L. Huang, Y. C. Chang, C. H. Chang, Y. J. Lee, P. Chang, J. Kwo, T. B. Wu, and M. Hong, "Surface passivation of III-V compound semiconductors using atomic-layer-deposition-grown Al2O3," Appl. Phys. Lett., vol. 87, p. 252104, 2005.
[45] C. H. Chang, Y. K. Chiou, Y. C. Chang, K. Y. Lee, T. D. Lin, T. B. Wu, M. Hong, and J. Kwo, "Interfacial self-cleaning in atomic layer deposition of HfO2 gate dielectric on In0.15Ga0.85As," Appl. Phys. Lett., vol. 89, p. 242911, 2006.
[46] Y. Xuan, Y. Q. Wu, T. Shen, T. Yang, and P. D. Ye, "High performance submicron inversion-type enhancement-mode InGaAs MOSFETs with ALD Al2O3, HfO2, and HfAlO as gate dielectrics," in Tech. Dig. - Int. Electron Devices Meet., 2007, pp. 637-640.
[47] Y. C. Chang, M. L. Huang, K. Y. Lee, Y. J. Lee, T. D. Lin, M. Hong, J. Kwo, T. S. Lay, C. C. Liao, and K. Y. Cheng, "Atomic-layer-deposited HfO2 on In0.53Ga0.47As: Passivation and energy-band parameters," Appl. Phys. Lett., vol. 92, p. 072901, 2008.
[48] H. C. Chin, M. Zhu, G. S. Samudra, and Y. C. Yeo, "n-channel GaAs MOSFET with TaN/HfAlO gate stack formed using in situ vacuum anneal and silane passivation," J. Electrochem. Soc., vol. 155, pp. H464-H468, 2008.
[49] J. Q. Lin, S. J. Lee, H. J. Oh, G. Q. Lo, D. L. Kwong, and D. Z. Chi, "Inversion-mode self-aligned In0.53Ga0.47As N-channel metal-oxide- semiconductor field-effect transistor with HfAlO gate dielectric and TaN metal gate," IEEE Electron Device Lett., vol. 29, pp. 977-980, 2008.
[50] S. Koveshnikov, N. Goel, P. Majhi, H. Wen, M. B. Santos, S. Oktyabrsky, V. Tokranov, R. Kambhampati, R. Moore, F. Zhu, et al., "In0.53Ga0.47As based metal oxide semiconductor capacitors with atomic layer deposition ZrO2 gate oxide demonstrating low gate leakage current and equivalent oxide thickness less than 1 nm," Appl. Phys. Lett., vol. 92, p. 222904, 2008.
[51] S. Koveshnikov, W. Tsai, I. Ok, J. C. Lee, V. Torkanov, M. Yakimov, and S. Oktyabrsky, "Metal-oxide-semiconductor capacitors on GaAs with high-k gate oxide and amorphous silicon interface passivation layer," Appl. Phys. Lett., vol. 88, p. 022106, 2006.
[52] J. P. de Souza, E. Kiewra, Y. Sun, A. Callegari, D. K. Sadana, G. Shahidi, D. J. Webb, J. Fompeyrine, R. Germann, C. Rossel, et al., "Inversion mode n-channel GaAs field effect transistor with high-k/metal gate," Appl. Phys. Lett., vol. 92, p. 153508, 2008.
[53] H.-S. Kim, I. Ok, M. Zhang, T. Lee, F. Zhu, L. Yu, J. C. Lee, S. Koveshnikov, W. Tsai, V. Tokranov, et al., "Depletion-mode GaAs metal-oxide-semiconductor field-effect transistor with HfO2 dielectric and germanium interfacial passivation layer," Appl. Phys. Lett., vol. 89, p. 222904, 2006.
[54] F. Gao, S. J. Lee, R. Li, S. J. Whang, S. Balakumar, D. Z. Chi, C. C. Kean, S. Vicknesh, C. H. Tung, D. L. Kwong, et al., "GaAs p- and n-MOS devices integrated with novel passivation (plasma nitridation and AIN-surface passivation) techniques and ALD-HfO2/TaN gate stack," in Tech. Dig. - Int. Electron Devices Meet., 2006, pp. 583-586.
[55] J. Kwo, D. W. Murphy, M. Hong, J. P. Mannaerts, R. L. Opila, R. L. Masaitis, and A. M. Sergent, "Passivation of GaAs using gallium-gadolinium oxides," J. Vac. Sci. Technol. B, vol. 17, pp. 1294-1296, 1999.
[56] M. Hong, Z. H. Lu, J. Kwo, A. R. Kortan, J. P. Mannaerts, J. J. Krajewski, K. C. Hsieh, L. J. Chou, and K. Y. Cheng, "Initial growth of Ga2O3(Gd2O3) on GaAs: Key to the attainment of a low interfacial density of states," Appl. Phys. Lett., vol. 76, pp. 312-314, 2000.
[57] M. L. Huang, Y. C. Chang, C. H. Chang, T. D. Lin, J. Kwo, T. B. Wu, and M. Hong, "Energy-band parameters of atomic-layer-deposition Al2O3/InGaAs heterostructure," Appl. Phys. Lett., vol. 89, p. 012903, 2006.
[58] K. Y. Lee, Y. J. Lee, P. Chang, M. L. Huang, Y. C. Chang, M. Hong, and J. Kwo, "Achieving 1 nm capacitive effective thickness in atomic layer deposited HfO2 on In0.53Ga0.47As," Appl. Phys. Lett., vol. 92, p. 252908, 2008.
[59] M. Hong, W. C. Lee, M. L. Huang, Y. C. Chang, T. D. Lin, Y. J. Lee, J. Kwo, C. H. Hsu, and H. Y. Lee, "Defining new frontiers in electronic devices with high κ dielectrics and interfacial engineering," Thin Solid Films, vol. 515, pp. 5581-5586, 2007.
[60] M. W. Hong, J. R. Kwo, P. C. Tsai, Y. C. Chang, M. L. Huang, C. P. Chen, and T. D. Lin, "III-V metal-oxide-semiconductor field-effect transistors with high κ dielectrics," Jpn. J. Appl. Phys, vol. 46, pp. 3167-3180, 2007.
[61] J. Kwo and M. Hong, "Research advances on III-V MOSFET electronics beyond Si CMOS," J. Cryst. Growth, vol. 311, pp. 1944-1949, 2009.
[62] R. M. Wallace, P. C. McIntyre, J. Kim, and Y. Nishi, "Atomic layer deposition of dielectrics on Ge and III-V Materials for ultrahigh performance transistors," MRS Bull., vol. 34, pp. 493-503, 2009.
[63] M. Houssa, E. Chagarov, and A. Kummel, "Surface defects and passivation of Ge and III-V Interfaces," MRS Bull., vol. 34, pp. 504-513, 2009.
[64] M. Hong, J. Kwo, T. D. Lin, and M. L. Huang, "InGaAs metal-oxide- semiconductor devices with Ga2O3(Gd2O3) high κ dielectrics for science and technology beyond Si CMOS," MRS Bull., vol. 34, pp. 514-521, 2009.
[65] M. Caymax, G. Brammertz, A. Delabie, S. Sioncke, D. Lin, M. Scarrozza, G. Pourtois, W. E. Wang, M. Meuris, and M. Heyns, "Interfaces of high-κ dielectrics on GaAs: Their common features and the relationship with Fermi level pinning," Microelectron. Eng., vol. 86, pp. 1529-1535, 2009.
[66] P. C. McIntyre, Y. Oshima, E. Kim, and K. C. Saraswat, "Interface studies of ALD-grown metal oxide insulators on Ge and III-V semiconductors," Microelectron. Eng., vol. 86, pp. 1536-1539, 2009.
[67] W. Tsai, N. Goel, S. Koveshnikov, P. Majhi, and W. Wang, "Challenges of integration of high-κ dielectric with III-V materials," Microelectron. Eng., vol. 86, pp. 1540-1543, 2009.
[68] J. Robertson, "Interface states model for III-V oxide interfaces," Microelectron. Eng., vol. 86, pp. 1558-1560, JUL-SEP 2009.
[69] S. Oktyabrsky and P. Ye, Eds., Fundamentals of III-V Semiconductor MOSFETs. Springer US, 2010.
[70] N. Goel, P. Majhi, C. O. Chui, W. Tsai, D. Choi, and J. S. Harris, "InGaAs metal-oxide-semiconductor capacitors with HfO2 gate dielectric grown by atomic-layer deposition," Appl. Phys. Lett., vol. 89, p. 163517, 2006.
[71] Y. Xuan, H.-C. Lin, and P. D. Ye, "Simplified surface preparation for GaAs passivation using atomic layer-deposited high-κ dielectrics," IEEE Trans. Electron Devices, vol. 54, pp. 1811-1817, 2007.
[72] K. H. Shiu, T. H. Chiang, P. Chang, L. T. Tung, M. Hong, J. Kwo, and W. Tsai, "1 nm equivalent oxide thickness in Ga2O3(Gd2O3)/In0.2Ga0.8As metal-oxide- semiconductor capacitors," Appl. Phys. Lett., vol. 92, p. 172904, 2008.
[73] F. Ren, M. W. Hong, W. S. Hobson, J. M. Kuo, J. R. Lothian, J. P. Mannaerts, J. Kwo, Y. K. Chen, and A. Y. Cho, "Enhancement-mode p-channel GaAs MOSFETs on semi-insulating substrates," in Tech. Dig. - Int. Electron Devices Meet., 1996, pp. 943-945.
[74] F. Ren, M. Hong, W. S. Hobson, J. M. Kuo, J. R. Lothian, J. P. Mannaerts, J. Kwo, S. N. G. Chu, Y. K. Chen, and A. Y. Cho, "Demonstration of enhancement-mode p- and n-channel GaAs MOSFETs with Ga2O3(Gd2O3) as gate oxide," Solid-State Electron., vol. 41, pp. 1751-1753, 1997.
[75] F. Ren, J. M. Kuo, M. Hong, W. S. Hobson, J. R. Lothian, J. Lin, H. S. Tsai, J. P. Mannaerts, J. Kwo, S. N. G. Chu, et al., "Ga2O3(Gd2O3)/InGaAs enhancement- mode n-channel MOSFETs," IEEE Electron Device Lett., vol. 19, pp. 309-311, 1998.
[76] Y. C. Wang, M. Hong, J. M. Kuo, J. P. Mannaerts, J. Kwo, H. S. Tsai, J. J. Krajewski, J. S. Weiner, Y. K. Chen, and A. Y. Cho, "Advances in GaAs MOSFETs Using Ga2O3(Gd2O3) as Gate Oxide," in Mat. Res. Soc. Symp. Proc. vol. 573, 1999, pp. 219-225.
[77] Y. Xuan, H. C. Lin, P. D. Ye, and G. D. Wilk, "Capacitance-voltage studies on enhancement-mode InGaAs metal-oxide-semiconductor field-effect transistor using atomic-layer-deposited Al2O3 gate dielectric," Appl. Phys. Lett., vol. 88, p. 263518, 2006.
[78] Y. Xuan, Y. Q. Wu, H. C. Lin, T. Shen, and P. D. Ye, "Submicrometer inversion-type enhancement-mode InGaAs MOSFET with atomic-layer- deposited Al2O3 as gate dielectric," IEEE Electron Device Lett., vol. 28, pp. 935-938, 2007.
[79] Y. Xuan, Y. Q. Wu, and P. D. Ye, "High-performance inversion-type enhancement-mode InGaAs MOSFET with maximum drain current exceeding 1 A/mm," IEEE Electron Device Lett., vol. 29, pp. 294-296, 2008.
[80] H. C. Chiu, T. D. Lin, P. Chang, W. C. Lee, C. H. Chiang, J. Kwo, Y. S. Lin, S. S. H. Hsu, T. W., and M. Hong, "Self-aligned Inversion Channel In0.53Ga0.47As N-MOSFETs with ALD-Al2O3 and MBE-Al2O3/Ga2O3(Gd2O3) as Gate Dielectrics," in International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2009, pp. 141-142.
[81] H. C. Chiu, P. Chang, M. L. Huang, T. D. Lin, Y. H. Chang, J. C. Huang, S. Z. Chen, J. Kwo, W. Tsai, and M. Hong, "High performance self-aligned inversion-channel MOSFETs with In0.53Ga0.47As channel and ALD-Al2O3," in 67th Device Res. Conf. Dig., 2009, pp. 83-84.
[82] H. C. Lin, W. E. Wang, G. Brammertz, M. Meuris, and M. Heyns, "Electrical study of sulfur passivated In0.53Ga0.47As MOS capacitor and transistor with ALD Al2O3 as gate insulator," Microelectron. Eng., vol. 86, pp. 1554-1557, 2009.
[83] D. Shahrjerdi, T. Rotter, G. Balakrishnan, D. Huffaker, E. Tutuc, and S. K. Banerjee, "Fabrication of self-aligned enhancement-mode In0.53Ga0.47As MOSFETs with TaN/HfO2/AlN gate stack," IEEE Electron Device Lett., vol. 29, pp. 557-560, 2008.
[84] A. M. Sonnet, C. L. Hinkle, M. N. Jivani, R. A. Chapman, G. P. Pollack, R. M. Wallace, and E. M. Vogel, "Performance enhancement of n-channel inversion type InxGa1-xAs metal-oxide-semiconductor field effect transistor using ex situ deposited thin amorphous silicon layer," Appl. Phys. Lett., vol. 93, p. 122109, 2008.
[85] H.-S. Kim, I. Ok, F. Zhu, M. Zhang, S. Park, J. Yum, H. Zhao, P. Majhi, D. I. Garcia-Gutierrez, N. Goel, et al., "High mobility HfO2-based In0.53Ga0.47As n-channel metal-oxide-semiconductor field effect transistors using a germanium interfacial passivation layer," Appl. Phys. Lett., vol. 93, p. 132902, 2008.
[86] M. Passlack, K. Rajagopalan, J. Abrokwah, and R. Droopad, "Implant-free high-mobility flatband MOSFET: principles of operation," IEEE Trans. Electron Devices, vol. 53, pp. 2454-2459, 2006.
[87] K. Rajagopalan, J. Abrokwah, R. Droopad, and M. Passlack, "Enhancement- mode GaAs n-channel MOSFET," IEEE Electron Device Lett., vol. 27, pp. 959-962, 2006.
[88] K. Rajagopalan, R. Droopad, J. Abrokwah, P. Zurcher, P. Fejes, and M. Passlack, "1-um Enhancement Mode GaAs N-channel MOSFETs with Transconductance Exceeding 250 mS/mm," IEEE Electron Device Lett., vol. 28, pp. 100-102, 2007.
[89] R. J. W. Hill, D. A. J. Moran, X. Li, H. Zhou, D. Macintyre, S. Thoms, A. Asenov, P. Zurcher, K. Rajagopalan, J. Abrokwah, et al., "Enhancement-mode GaAs MOSFETs with an In0.3Ga0.7As channel, a mobility of over 5000 cm2/Vs, and transconductance of over 475 mS/mm," IEEE Electron Device Lett., vol. 28, pp. 1080-1082, 2007.
[90] Y. Sun, E. W. Kiewra, S. J. Koester, N. Ruiz, A. Callegari, K. E. Fogel, D. K. Sadana, J. Fompeyrine, D. J. Webb, J. P. Locquet, et al., "Enhancement-mode buried-channel In0.7Ga0.3As/In0.52Al0.48As MOSFETs with high-k gate dielectrics," IEEE Electron Device Lett., vol. 28, pp. 473-475, 2007.
[91] Y. Sun, E. W. Kiewra, J. P. de Souza, J. J. Bucchignano, K. E. Fogel, D. K. Sadana, and G. G. Shahidi, "Scaling of In0.7Ga0.3As buried-channel MOSFETs," in Tech. Dig. - Int. Electron Devices Meet., 2008, pp. 367-370.
[92] C. P. Chen, T. D. Lin, Y. J. Lee, Y. C. Chang, M. Hong, and J. Kwo, "Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal-oxide- semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric," Solid-State Electron., vol. 52, pp. 1615-1618, 2008.
[93] J. F. Ziegler. James Ziegler - SRIM & TRIM. Available: http://www.srim.org/
[94] J. F. Ziegler, M. D. Ziegler, and J. P. Biersack, "SRIM - The stopping and range of ions in matter (2010)," Nucl. Instr. Meth. B, vol. 268, pp. 1818-1823, 2010.
[95] C. P. Chen, Y. J. Lee, Y. C. Chang, Z. K. Yang, M. Hong, J. Kwo, H. Y. Lee, and T. S. Lay, "Structural and electrical characteristics of Ga2O3(Gd2O3)/GaAs under high temperature annealing," J. Appl. Phys., vol. 100, p. 104502, 2006.
[96] Y. L. Huang, P. Chang, Z. K. Yang, Y. J. Lee, H. Y. Lee, H. J. Liu, J. Kwo, J. P. Mannaerts, and M. Hong, "Thermodynamic stability of Ga2O3(Gd2O3)/GaAs interface," Appl. Phys. Lett., vol. 86, p. 191905, 2005.
[97] T. D. Lin, "Progress report," Advanced Nano Thin Film Epitaxy Lab, Hsinchu, Taiwan, Dec. 25, 2006.
[98] J. F. Zheng, W. Tsai, T. D. Lin, Y. J. Lee, C. P. Chen, M. Hong, J. Kwo, S. Cui, and T. P. Ma, "Ga2O3(Gd2O3)/Si3N4 dual-layer gate dielectric for InGaAs enhancement mode metal-oxide-semiconductor field-effect transistor with channel inversion," Appl. Phys. Lett., vol. 91, p. 223502, 2007.
[99] T. P. Ma, "Making silicon nitride film a viable gate dielectric," IEEE Trans. Electron Devices, vol. 45, pp. 680-690, 1998.
[100] T. D. Lin, C. P. Chen, M. L. Huang, Y. J. Lee, C. H. Lee, M. C. Pan, M. Hong, J. Kwo, J. F. Zheng, W. Tsai, et al., "Growth and material characteristics of Ga2O3(Gd2O3)/Si3N4 dual-layer gate dielectric for inversion-channel and depletion mode GaAs-based MOSFET," presented at the MRS Spring Meeting, 2007.
[101] K. H. Shiu, C. H. Chiang, Y. J. Lee, W. C. Lee, P. Chang, L. T. Tung, M. Hong, J. Kwo, and W. Tsai, "Oxide scalability in Al2O3/Ga2O3(Gd2O3)/In0.20Ga0.80As/ GaAs heterostructures," J. Vac. Sci. Technol. B, vol. 26, pp. 1132-1135, 2008.
[102] B. Yang, P. D. Ye, J. Kwo, M. R. Frei, H. J. L. Gossmann, J. P. Mannaerts, M. Sergent, M. Hong, K. Ng, and J. Bude, "Impact of metal/oxide interface on DC and RF performance of depletion-mode GaAs MOSFET employing MBE grown Ga2O3(Gd2O3) as gate dielectric," J. Cryst. Growth, vol. 251, pp. 837-842, 2003.
[103] Y. Xuan, T. Shen, M. Xu, Y. Q. Wu, and P. D. Ye, "High-performance surface channel In-rich In0.75Ga0.25As MOSFETs with ALD high-κ as gate dielectric," in Tech. Dig. - Int. Electron Devices Meet., 2008, pp. 371-374.
[104] Y. D. Wu, T. D. Lin, T. H. Chiang, Y. C. Chang, H. C. Chiu, Y. J. Lee, M. Hong, C. A. Lin, and J. Kwo, "Engineering of threshold voltages in molecular beam epitaxy-grown Al2O3/Ga2O3(Gd2O3)/In0.2Ga0.8As," J. Vac. Sci. Technol. B, vol. 28, pp. C3H10-C3H13, 2010.
[105] T. D. Lin, Y. D. Wu, Y. C. Chang, T. H. Chiang, C. Y. Chuang, C. A. Lin, W. H. Chang, H. C. Chiu, W. Tsai, J. Kwo, et al., "Achieving nearly free Fermi-level movement and Vth Engineering in Ga2O3(Gd2O3)/In0.2Ga0.8As," in 67th Device Res. Conf. Dig., 2009, pp. 127-128.
[106] T. D. Lin, H. C. Chiu, P. Chang, L. T. Tung, C. P. Chen, M. Hong, J. Kwo, W. Tsai, and Y. C. Wang, "High-performance self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistor with Al2O3/ Ga2O3(Gd2O3) as gate dielectrics," Appl. Phys. Lett., vol. 93, p. 033516, 2008.
[107] T. D. Lin, P. Chang, H. C. Chiu, M. Hong, J. Kwo, Y. S. Lin, and S. S. H. Hsu, "dc and rf characteristics of self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect transistors using molecular beam epitaxy-Al2O3/Ga2O3(Gd2O3) as gate dielectrics," J. Vac. Sci. Technol. B, vol. 28, pp. C3H14-C3H17, 2010.
[108] D. K. Schroder, "MOSFET Mobility," in Semiconductor Material and Device Characterization, 3rd ed Hoboken, New Jersey: John Wiley and Sons, Inc., 2005, pp. 489-503.
[109] T. D. Lin, H. C. Chiu, P. Chang, W. C. Lee, T. H. Chiang, J. R. Kwo, W. Tsai, and M. Hong, "InGaAs MOSCAPs and self-aligned inversion-channel MOSFETs with Al2O3/Ga2O3(Gd2O3) as a gate dielectric," ECS Trans., vol. 19, pp. 351-360, 2009.
[110] D.-H. Kim and J. A. del Alamo, "30-nm InAs Pseudomorphic HEMTs on an InP Substrate With a Current-Gain Cutoff Frequency of 628 GHz," IEEE Electron Device Lett., vol. 29, pp. 830-833, 2008.
[111] M. Passlack, P. Zurcher, K. Rajagopalan, R. Droopad, J. Abrokwah, M. Tutt, Y.-B. Park, E. Johnson, O. Hartin, A. Zlotnicka, et al., "High mobility III-V MOSFETs for rf and digital applications," in Tech. Dig. - Int. Electron Devices Meet., 2007, pp.621-624.
[112] C. Y. Chan, S. C. Chen, M. H. Tsai, and S. Hsu, "Wiring Effect Optimization in 65-nm Low-Power NMOS," IEEE Electron Device Lett., vol. 29, pp. 1245-1248, 2008.
[113] Y. Q. Wu, W. K. Wang, O. Koybasi, D. N. Zakharov, E. A. Stach, S. Nakahara, J. C. M. Hwang, and P. D. Ye, "0.8-V supply voltage deep-submicrometer inversion-mode In0.75Ga0.25As MOSFET," IEEE Electron Device Lett., vol. 30, pp. 700-702, 2009.
[114] Y. Q. Wu, M. Xu, R. S. Wang, O. Koybasi, and P. D. Ye, "High performance deep-submicron inversion-mode InGaAs MOSFETs with maximum Gm exceeding 1.1 mS/mm: new HBr pretreatment and channel engineering," Tech. Dig. - Int. Electron Devices Meet., 2009, pp. 296-299.
[115] T. D. Lin, H. C. Chiu, P. Chang, Y. H. Chang, Y. D. Wu, M. Hong, and J. Kwo, "Self-aligned inversion-channel In0.75Ga0.25As metal-oxide-semiconductor field- effect-transistors using UHV-Al2O3/Ga2O3(Gd2O3) and ALD-Al2O3 as gate dielectrics," Solid-State Electron., vol. 54, pp. 915-924, 2010.
[116] H. C. Chiu, L. T. Tung, Y. H. Chang, Y. J. Lee, C. C. Chang, J. Kwo, and M. Hong, "Achieving a low interfacial density of states in atomic layer deposited Al2O3 on In0.53Ga0.47As," Appl. Phys. Lett., vol. 93, p. 202903, 2008.
[117] P. D. Ye, "Main determinants for III-V metal-oxide-semiconductor field-effect transistors," J. Vac. Sci. Technol. A, vol. 26, pp. 697-704, 2008.
[118] Y. Q. Wu, R. S. Wang, T. Shen, G. J. J., and P. D. Ye, "First experimental demonstration of 100 nm Inversion-mode InGaAs FinFET through damage-free sidewall etching," Tech. Dig. - Int. Electron Devices Meet, pp. 331-334, 2009.
[119] H. C. Chin, X. Gong, X. K. Liu, and Y. C. Yeo, "Lattice-mismatched In0.4Ga0.6As source/drain stressors with in situ doping for strained In0.53Ga0.47As Channel n-MOSFETs," IEEE Electron Device Lett., vol. 30, pp. 805-807, Aug 2009.
[120] T. D. Lin, P. Chang, Y. D. Wu, H. C. Chiu, J. Kwo, and M. Hong, "Achieving very high drain current of 1.23 mA/μm in a 1μm-gate-length self-aligned inversion-channel MBE-Al2O3/Ga2O3(Gd2O3)/In0.75Ga0.25As MOSFET," submitted to J. Cryst. Growth.
[121] M. Radosavljevic, B. Chu-Kung, S. Corcoran, G. Dewey, M. K. Hudait, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, M. Metz, et al., "Advanced high-k gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications " in Tech. Dig. - Int. Electron Devices Meet., 2009, pp. 319-322.