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研究生: 顏如敏
Ju-Min Yen
論文名稱: TFT Array廠在光罩限制下之現場排程問題
Shop Floor Scheduling Problems Considering Mask Constraints in TFT Array Process
指導教授: 林則孟
James T. Lin
口試委員:
學位類別: 碩士
Master
系所名稱: 工學院 - 工業工程與工程管理學系
Department of Industrial Engineering and Engineering Management
論文出版年: 2006
畢業學年度: 94
語文別: 中文
論文頁數: 126
中文關鍵詞: 陣列廠迴流光罩投料現場排程
外文關鍵詞: TFT Array, re-entrant process, masks allocation, shop floor scheduling
相關次數: 點閱:3下載:0
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  • TFT-LCD(thin film transistor-liquid crystal display)面板由薄膜電晶體(TFT Array)、面板組立(Cell)及模組(Module)三大製程所構成,其中以TFT Array製程為最重要。由於TFT Array製程為三段製程之首,且因製程時間最長、機台設備最為昂貴,成為TFT-LCD製程的瓶頸所在。TFT Array製程的產出情形對整個生產鏈有重要的影響,若未能達到生產規劃部門所制定的產出計畫,將使後續製程發生缺料的狀況。因此,為能達成日產出計畫及提昇瓶頸產能的利用率,TFT Array需要一能同時考量此兩項目標的投料計畫。
    TFT Array製程具有許多特性與限制,使其現場排程問題變得相當複雜。TFT Array製具有受限產能迴流的特性,再加上其中的瓶頸黃光製程需使用除機台之外的副資源—光罩,每種產品的各迴流層都有其專屬的光罩,且光罩與瓶頸機台之間有一特定的搭配限制。同時,因為光罩成本昂貴,光罩數量也成為在排程上需考量的限制。在迴流、光罩與機台搭配關係及光罩數量限制的特性下,造成TFT Array的現場排程問題變得相當複雜。針對此些特性及生產排程考量的目標,本研究提出一考量光罩限制的兩階段排程法。在第一階段優先處理光罩與瓶頸機台的配置問題,並作為第二階段瓶頸作業排程時的輸入資訊;第二階段則是以DBR排程方法精神為基的瓶頸作業排程,以求得適宜的投料計畫。
    藉由實驗設計與模擬分析發現,本研究所提的兩階段排程方法能迅速解決現今TFT Array作排程時所面臨到的難題,且在延遲時間及瓶頸機台使用率的表現呈現良好的結果,可輔助TFT Array廠作投料規劃時使用。


    A TFT-LCD (thin film transistor-liquid crystal display) manufacturing consists of three main processes: TFT Array, Cell and Module process, and TFT Array is the most important of all. Being the first manufacturing stage, the throughput of TFT Array has a significant impact on the subsequent processes. In order to prevent material shortages in Cell plants, TFT Array plants must produce the right products with correct quantities to comply with the daily throughput schedule. In addition, the resource utilization in TFT Array process has been placed high attention due to expensive equipments. As a result, an effective release plan is necessitated for TFT Array process to achieve the daily throughput schedule and simultaneously exploit the finite resource.
    Many manufacturing characteristics and constraints in TFT Array process lead to a great complexity in TFT Array shop floor scheduling. Firstly, TFT Array process is a re-entrant flow, in which a similar sequence of processing step is repeated for five times. Further, the photolithography stage, the bottleneck in TFT Array process, requires a second resource in addition to machines (steppers or scanners). Photo masks and scanners are both indispensable while executing exposure operation in the photolithography stage. Every product with different re-entrant layer requires a unique mask and consequently each has a set of mask with five different pieces. Moreover, there is a tool eligibility issue between masks and scanners. Masks are approved to be used in specific scanners for quality considerations. Since TFT Array process is characterized as reentry and mask constraints, it is regarded as a complicated scheduling problem and is more difficult to solve than classical ones.
    In this study, we decompose the complex problems and present a two-phase scheduling method to acquire a suitable release plan for TFT Array process, which are masks allocation and a DBR-based bottleneck operations scheduling. In the first phase, masks allocation problem is quickly solved by mathematical programming and each mask is designated to one or more scanners. Phase one is similar to a rough-cut capacity planning. Afterward the detail bottleneck operations scheduling and the release plan is established according to DBR (drum-buffer-rope) scheduling method in accordance with the mask allocation result from the previous phase.
    Finally, relative scheduling performances of the two-phase scheduling method are provided by a simulation model extracting from a real TFT-LCD manufacturing company. The release plans developed for the tardiness and resource utilization criteria reveal that the proposed methodology quickly solves the difficult scheduling problem and performs well.

    第一章 緒論 1 1.1 研究背景與動機 1 1.2 研究目的 2 1.3 研究範圍與限制 2 1.4 研究步驟與方法 3 第二章 TFT Array生產系統特性分析 5 2.1 薄膜電晶體構造與製程介紹 5 2.1.1 薄膜製程(Thin Film Process) 8 2.2.1.1 清洗加工站 8 2.2.1.2 成膜製程 9 2.1.2 黃光製程(Photolithography Process) 10 2.1.2.1 光阻塗佈作業 11 2.1.2.2 曝光作業 12 2.1.2.3 顯影作業 12 2.1.3 蝕刻製程(Etching Process) 12 2.1.4 剝膜製程(Stripping Process) 13 2.1.5 ADI檢測站 14 2.1.6 Array最終檢測 14 2.2 TFT Array生產系統特性分析 14 2.2.1 生產系統特性說明 14 2.2.2 瓶頸機台特性說明 15 2.2.3 非瓶頸機台特性說明 18 2.3 TFT Array系統排程特色分析 19 2.4 研究問題定義 22 2.4.1 研究問題說明與定義 22 2.4.2 假設條件 23 2.4.3 績效指標 24 第三章 文獻回顧 26 3.1 迴流製程現場排程相關文獻 26 3.2 半導體現場排程相關文獻 27 3.2.1 投料問題 27 3.2.2 派工問題 28 3.2.3 結合投料與派工問題 30 3.3 TFT Array現場排程問題 32 第四章 考量光罩限制之兩階段現場排程方法 34 4.1 研究方法架構 34 4.1.1 光罩與瓶頸機台配置 35 4.1.2 投料與派工 36 4.2 階段一:光罩與瓶頸機台配置數學規劃模式 38 4.2.1 確認瓶頸資源相關資訊 41 4.2.2 訂定初始排程長度 41 4.2.3 彙整產出需求 42 4.2.4 計算光罩負荷 43 4.2.5 建構光罩與瓶頸機台配置數學模式與求解 44 4.3 階段二:以DBR為基的瓶頸作業排程 48 4.3.1 訂定初始緩衝值 52 4.3.2 計算各瓶頸作業理想的開始與結束時間 54 4.3.3 產生廢墟—分派各瓶頸作業至瓶頸機台 56 4.3.4 產生限制驅導節奏—產生各瓶頸作業的開始與結束時間 60 4.3.5 填補產能空洞 67 4.3.6 產生投料計畫與預期完成時間 70 第五章 TFT Array廠兩階段排程法實驗模擬分析 72 5.1 模擬實驗的目的 72 5.2 實驗架構 74 5.2.1 環境因子 75 5.2.2 控制因子 76 5.2.3 模擬蒐集之績效指標 76 5.3 系統描述與假設 77 5.3.1 系統描述 77 5.3.2 基本資料輸入 78 5.4 範圍與細緻度 82 5.4.1 系統個體訂定(Entity) 83 5.4.2 活動組成與行為訂定(Resource & Control) 83 5.5 模擬模式構建 91 5.5.1 模式建構 91 5.5.2 模式確認與驗證 93 5.5.3 模擬實驗的進行 94 5.6 模擬實驗結果分析 95 5.6.1 實驗分析步驟 95 5.6.2 實驗分析結果 96 5.7 小結 105 第六章 結論與建議 108 6.1 結論 108 6.2 建議 108 參考文獻 110 附錄一 因子與因子之間交互作用變異數分析表 115 附錄二 單因子變異數分析表 122 附錄三 Finsher LSD Test分析表 124

    1.吳鴻輝、李榮貴,限制驅導式現場排程與管理技術,全華科技圖書服份有限公司,1999。
    2.林則孟,「系統模擬理論與應用」,滄海書局,2001。
    3.林則孟,「生產計畫與管理」,華泰文化,2006。
    4.陳亞妮,「薄膜電晶體陣列廠生產規劃系統之建構」,交通大學工業工程與管理所碩士論文,2004。
    5.游淑晴,「黃光區關鍵層機台限制機台指派投料與派工法則探討」,國立清華大學工業工程與工程管理研究所碩士論文,2003。
    6.張永政,「半導體廠綁機情境下之投料與派工」,國立交通大學工業工程與管理學系碩士論文,2003。
    7.黎翠綾,「在機台群組限制下的黃光區投料派工模式」,國立交通大學工業工程與管理學系碩士論文,1999。
    8.簡秀安,「TFT-LCD產業陣列製程投料機制之建構與績效分析」,東海大學工業工程與經營資訊研究所碩士論文,2004。
    9.蘇志浩,「以限制驅導式為基之半導體最終測試廠短期生產排程模式」,國立清華大學碩士論文,1999。
    10.Akcalt, E., Nemoto, K., and Uzsoy, R., “Cycle-Time Improvements for Photolithography Process in Semiconductor Manufacturing,” IEEE Transaction on Semiconductor Manufacturing, Vol. 14, No.1, pp. 48~56, 2001.
    11.Blackstone, J. H., Phillips, D. T., and Hogg, G. L., “State-of-the-art Survey of Dispatching Rules for Manufactruing Job Shop Operation,” International Journal of Production Research, Vol. 20, pp. 27-45, 1982.
    12.Garrett, V. R., Sheldon, X. C. L., and Stanley, B. G., “Production Control for A Tandem Two-Machine System,” IIE Transactions, Vol. 25, No.5, 1993.
    13.Glassy, C. R. and Resende, M. G. C., “Closed-loop Job Release Control for VLSI Circuit Manufacturing”, IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No. 1, pp.26-48, 1988a.
    14.Glassy, C. R. and Resende, M. G. C., “A Scheduling Rule for Job Release in Semiconductor Fabrication,” Operation Research Letters, Vo7. 5, No. 1, pp.213-217, 1988b.
    15.Goldratt, E. M., “The Haystack Syndorme”, Croton-on-Hudson: North River, 1990.
    16.Hwang, H., Sun, J. U., “Production Sequencing Problem with Reentrant Work Flows and Sequence Dependent Setup Times,” International Journal of Production Research, Vol.36, No. 9, pp. 2435~2450.
    17.Kim, Y. D., Kim, J.U., Lim, S. K., “Due Date Based Scheduling and Control Policies in a Multi-Product Semiconductor Wafer Fabrication Facility,” IEEE Transaction on Semiconductor Manufacturing, Vol. 11, No.1, pp. 155~164, 1998a.
    18.Kim, Y. D., Lee, D., Kim, J.U., “A Simulation Study on Lot Release Control , Mask Scheduling and Batch Scheduling in Semiconductor Wafer Fabrication Facility,” Journal of Manufacturing Systems, Vol. 17, No. 2, pp.107~117, 1998b.
    19.Kumar, P. R. and Meyn, Sean P., “Stability of queueing networks and scheduling polices,” Proceedings of the IEEE Conference on Decision and Control, Vol. 3, pp. 2730~2735, 1993.
    20.Kumar, R., Tiwariz, M. K., and Alladay, V., “Modeling and Rescheduling of a Re-entrant Wafer Fabrication Line Involving Machine Unreliability,” International Journal of Production Research, Vol.42, No. 21, pp. 4431~4455, 2004.
    21.Lamba, N., Karimi, I. A., and Bhalla A., “Scheduling a Single-Product Reentrant Process with Uniform Processing Times,” Industry Engineering Chemistry Research, Vol. 39, pp. 4203~4214, 2000.
    22.Lee, Y. H. and Lee, B., “Push-Pull Production Planning of The Re-entrant Process,” International Journal of Advanced Manufacturing Technology, Vol. 22, No. 11~12, pp. 922~931, 2003.
    23.Lu, S. C., Ramaswamy, D. and Kumar, P. R., “Efficient Scheduling Policies to Redue Mean and Variance of Cycle Time in Semiconductor Plants,” IEEE Transaction on Semiconductor Manufacturing, Vol. 7, pp. 374~388, 1994.
    24.Lou, S., and Kager, P. W., “A Robust Production Control Policy for VLSI Wafer Fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. 2, pp. 3-9, 1990.
    25.Melnyk, S. A., and Ragatz, G. L., “Order Review/Release: Research Issues and Perspectives,” Inyrtnsyion Joutnsl of Production Research, Vol 27, pp.1081~1096, 1989.
    26.Miragliotta, G. and Perona, M., “Decentralised, Multi-Objective Driven Scheduling for Reentrant Shops: A Conceptual Development and A test Case”, European Journal of Operational Research, Vol. 167, No.3, pp.644-662, 2005.
    27.Nose, K., Hiramatsu, A., and Konishi, M., “Using Genetic Algorithm for Job-Shop Scheduling Problems with Reentrant Product Flows,” IEEE Symposium on Emerging Technologies and Factory Automation, ETFA, Vol. 2, pp. 1339~1346, 1999.
    28.Pearn, W. L., Chung, S. H., Chen, A. Y., and Yang, M. H, “A case study on the multistage IC final testing scheduling problem with reentry,” International Journal of Production Economics, Vol. 88, No.3, pp. 257~267, 2004.
    29.Schragenheim, E. and Renen, B., “Drum-buffer-rope Shop Floor Control,” Production and Inventory Management Journal, 3rd Quarter, Vol. 31, No. 3, pp.18~23, 1990.
    30.Schragenheim, E. and Renen, B., “Buffer Management. A Diagnostic Tool for Production Control,” Production and Inventory Management Journal, 2nd Quarter, Vol. 32, No. 2, pp.74~79, 1991.
    31.Spearman, M. L., Woodruff, D. L., and Hopp, W. J., “CONWIP: A Pull Alternative to Kanban,” International Journal of Production Research, Vol. 28, No. 5, pp. 879-894, 1990.
    32.Uzsoy, R., Church, L., Ovacik, I., “Performance Evaluation of Dispatching Rules for Semiconductor Testing Operations,” Journal of Electronics Manufacturing, Vol. 3, pp. 95~105, 1993.
    33.Uzsoy, R., Lee, C., Martin Vega, L., “A Review of Production Planning and Scheduling Models in the Semiconductor Industry, Part 1: System Characteristics, Performances Evaluation and Production Planning,” IIE Transaction, Vol. 24, pp.47~60, 1992.
    34.Vargas-Villamil, F. D., and Rivera, D. E., “Multilayer Optimization and Scheduling Using Model Predictive Control: Application to Reentrant Semiconductor Manufacturing,” Computers and Chemical Engineering, Vol. 24, pp. 2009~2021, 2000.
    35.Yura, K., “Cyclic Scheduling for Re-entrant Manufacturing Systems,” International Journal of Production Economics, Vol. 60-61, pp. 523~528, 1999.
    36.Wein, L. M., “Scheduling Semiconductor Wafer Fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. 1, pp.115-130, 1988.
    37.Wu, H. H. and Yeh, M.L., "A DBR Scheduling Method for Manufacturing Environments with Bottleneck Reentrant Flows," International Journal of Production Research, Vol. 44, No. 5, pp. 883-902, 2006.
    38.Wu, S. Y., Morris J. S., and Gordon T. M., “A Simulation Analysis of the Effectiveness of Drum-Buffer-Rope Scheduling in Furniture Manufacturing,” Computers and Engineering, Vol. 26, No. 4, pp. 757-764, 1994.
    39.Yan H., Lou, SXC, Sethi SP, Gardel A., and Deosthali P., “Testing the Robustness of Various Production Control Policies in Semiconductor Manufacturing,” IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 2, pp. 285-289, 1996.
    40.Zoghby, J., Barnes, J. W., and Hasenbein, J. J., "Modeling the Reentrant Job Shop Scheduling Problem with Setups for Metaheuristic Searches," European Journal of Operational Research, Vol. 167, pp. 336~348, 2005.

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