超大型積體電路晶片上的過大電流可以導致可靠度的問題，像是雜訊跟電源的消耗。在這篇論文，我們嘗試分析電路中最大瞬間電流的下限。電路中的最大瞬間電流主要包含開關電流跟漏電流。這篇論文的目的是尋找一組”最壞情況□的輸入向量，可以導致產生越多的邏輯閘開關動作越好。要產生越多的開關動作，我們把邏輯閘於某一時間點的切換條件規劃為一個布林函數稱為 TAF。藉由建造於某一時間點的一組邏輯閘集合的 TAF，我們可以使用 ATPG 或 SAT 來決定是不是這些邏輯閘集合可以在該時間有開關動作。此外，我們可以推導出一組輸入向量來產生這組邏輯閘集合的開關動作。我們的方法由上限計算工具的結果開始。然後遞迴地建造由上限結果工具產生可能導致最大瞬間電流的邏輯閘集合之TAF。我們的實驗結果顯示，這個使用 TAF 的新技術在 ISCAS 組合電路可以得到 30% 比基因演算法更精確的結果。另外，由於我們方法的天性，我們可以考慮穿過循序元件(正反器)的訊號關聯性，反之先前的這個主題相關研究只能使用在組合電路而已。我們的結果在 ISCAS 循序電路上可以得到比隨機模擬得到 58% 的改善。

Large current in a VLSI chip can cause reliability problems such as noises and power consumption. In this thesis, we attempt to analyze the lower bound on the Maximum Instantaneous Current (MIC) of a circuit. The MIC of a circuit mainly consists of switching and leakage current. The objective of this thesis is to find a pair of “worst-case” input vectors, which can activate as many switchings as possible. To activate many switchings, we formulate a gate’s rising conditions at a time instant as a Boolean function called the Transition-Aware Function (TAF). By constructing the TAFs of a time instant for a set of gates, we can use ATPG or SAT solver to determine whether the set of gates can switch at the time instant, and in addition, we can also derive a pair of input vectors to activate the set of gates. Our algorithm starts with solutions from upper-bound estimation tools in [2]. Then, recursively builds the TAFs for the set of gates reported to have large MIC from an upper bound tool. Our experimental results show that the new technique using the TAF can be 30% more accurate than the genetic algorithm in [4] for ISCAS combinational benchmarks. In addition, due to the nature of our algorithm, it also can consider signal correlations across sequential elements (flip-flops), whereas previous research on this topic addressed on combinational circuits only. Our results on ISCAS sequential benchmarks show 58% improvement than those from random simulation.

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