基於鏈結式直接記憶體存取控制器的低功耗多傳感器穿戴式醫療裝置設計與分析

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研究生：	沈友仁 Shen, You-Ren
論文名稱：	基於鏈結式直接記憶體存取控制器的低功耗多傳感器穿戴式醫療裝置設計與分析 Design and Analysis of a Low-Power Multi-Sensor Wearable Medical Device using Linked Direct Memory Access (LDMA) controller
指導教授：	周百祥 Chou, Pai H.
口試委員:	韓永楷 Hon, Wing-Kai 謝孫源 Hsieh, Sun-Yuan
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2021
畢業學年度：	109
語文別：	英文
論文頁數：	50
中文關鍵詞：	鏈結式直接記憶體存取控制器、低功耗、多傳感器、穿戴式醫療裝置
外文關鍵詞：	linked direct memory access (LDMA), wearable medical device, lower power, multi-sensor
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對於一個主要任務為監控與紀錄環境及生理資料的穿戴式醫療裝置而言，在要求多個感測器
以高採樣率收集資料的情況下，會對處理器使用率造成極大的負擔，可能會導致可排程性的
喪失。對於像資料蒐集這樣的規律性作業，本論文提出一種可以大幅減少處理器使用率的排
程設計，運用新型微控制器上所搭載的鏈結式直接記憶體存取(Linked DMA, LDMA)，將原
本由處理器所執行的一系列指令，儘可能交由LDMA去自動化完成，以實現一個低處理器使
用率的硬實時系統(hard real-time system)。在這樣的系統中，我們同時考慮LDMA 通道的使
用率，並嘗試了兩種設計: 處理器使用率最佳化設計及負載平衡設計。在處理器使用率最佳
化設計中，本論文將實例系統的六個任務中的四個任務轉換為可以完全交由LDMA控制器來
執行，而不需要處理器介入的形式，將原本處理器使用率為63.1%的系統降至了19.1%，並且
佔用了所有的LDMA通道。考量到LDMA通道也是一種有限資源，本論文提出了LDMA任務
排程器進行LDMA通道的資源分配，實現LDMA通道的重用性，並應用在負載平衡設計中，
大幅減少LDMA通道使用率。

This thesis presents a scheduling scheme that maximizes offloading of hard real-time tasks onto linked
direct memory access (LDMA) hardware on modern microcontroller units (MCU). These tasks are
characterized by data collection of vital signs that must be sampled at relative high rates but otherwise
have relatively low computation load to perform. Conventional processors are poorly matched
with such loads, because they must service parallel data-collection tasks by context switching among
them as triggered by either a timer or a data-ready interrupt, all without using the computing capability
of the processor. This thesis describes a case study of a wearable medical device that takes
full advantage of LDMA to achieve the most efficient implementation on the MCU. This thesis proposes
two designs: the processor-LDMA co-optimization design and the load-balancing design. The
processor-LDMA co-optimization design reduce the processor utilization from 63.1% to 19.1% with
LDMA channels fully occupied. This thesis also proposes the load-balancing design using our proposed
LDMA task scheduler to significantly reduce the LDMA channel utilization while maintaining
low processor utilization (19.2%).

Contents i
Acknowledgments vi
Introduction 1
1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Background and Related Work 4
1 Input/Output (I/O) Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Interrupt I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Enhanced DMA Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Designs Using Advanced DMA . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Processor-DMA Co-Scheduling . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Common Bus Protocols for Embedded Systems . . . . . . . . . . . . . . . . . . . . 7
3.1 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Inter-Integrated Circuit (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Real-Time Operating Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Types of Real-Time Systems . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Rate Monotonic Scheduling (RMS) . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Earliest Deadline First (EDF) . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.5 Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Motivating Example: BlueBox 13
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Sampling-Rate and Bit-Resolution Requirements . . . . . . . . . . . . . . . . . . . 16
Linked Direct Memory Access (LDMA) 17
1 Channel Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1 Types of Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 Descriptor Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.3 Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4 Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2 LDMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1 Trigger Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 Looping Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 Channel Mechanism Overview . . . . . . . . . . . . . . . . . . . . . . . . . 19
LDMA Task Scheduler 22
1 LDMA Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2 Multiplexing LDMA Channels Among LDMA Tasks . . . . . . . . . . . . . . . . . 23
3 The LDMA Task Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 Channel Allocation Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2 Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 Task Enter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5 Task Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.6 Task End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.7 Context Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.8 Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.9 Channel Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.10 Channel Schedulability Analysis . . . . . . . . . . . . . . . . . . . . . . . . 30
Evaluation 31
1 RTOS Applications of BlueBox . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.1 Task Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.2 Schedulability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.3 Task Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2 Converting RTOS tasks into LDMA tasks . . . . . . . . . . . . . . . . . . . . . . . 32
2.1 Loop Type and Non-loop Type . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2 ADS1298R-Sampling Task . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.3 LED Signal Control Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4 Data-Gathering Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.5 Flash-Writing Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3 Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.1 Processor-LDMA Co-Optimization Design . . . . . . . . . . . . . . . . . . 45
3.2 Load-Balancing Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Conclusions and Future Work 47
1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
                                

[1] Y. Bao and X. Jiang, “Design of data information acquisition system which based upon DMA
technology,” in 2009 Second International Symposium on Knowledge Acquisition and Modeling,
vol. 3, pp. 387–390, 2009.
[2] M. Prokin, “DMA transfer method for wide-range speed and frequency measurement,” IEEE
Transactions on Instrumentation and Measurement, vol. 42, no. 4, pp. 842–846, 1993.
[3] S. Ma, L. Huang, Y. Lei, Y. Guo, and Z. Wang, “An efficient direct memory access (DMA)
controller for scientific computing accelerators,” in 2019 IEEE International Symposium on
Circuits and Systems (ISCAS), pp. 1–5, 2019.
[4] T. INSTRUMENTS, KeyStone Architecture Enhanced Direct Memory Access (EDMA3) Controller
User’s Guide. TEXAS INSTRUMENTS, 2015.
[5] F. Chen, L. Fei, and C. Duan, “The application of EDMA in TD-LTE-A system,” in 2013 2nd International
Symposium on Instrumentation and Measurement, Sensor Network and Automation
(IMSNA), pp. 972–974, 2013.
[6] R. Madhuri, M. M. Hampali, N. Umesh, K. Pooja, Y. J. M. Shirur, and V. S. Chakravarthi,
“Design and implementation of edma controller for ai based dsp socs for real- time multimedia
processing,” in 2020 Fourth International Conference on I-SMAC (IoT in Social, Mobile,
Analytics and Cloud) (I-SMAC), pp. 554–563, 2020.
[7] Y.-Z. Wu, “Synthesis of the hardware/software interface in microcontroller-based systems,” in
Performance Optimization with Linked DMA and RTOS for Wearable Multi-Modality Medical
Devices, (National Tsing Hua University), 2020.
[8] S. Wasly and R. Pellizzoni, “Hiding memory latency using fixed priority scheduling,” in 2014
IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 75–
86, 2014.
[9] S.-L. Tan and T. N. B. Anh, “Real-time operating system (RTOS) for small (16-bit) microcontroller,”
in 2009 IEEE 13th International Symposium on Consumer Electronics, pp. 1007–1011,
2009.
[10] X. Wang, X. Tong, and X. Du, “Research and implement of dynamic hybrid real-time tasks
scheduling algorithm based on μc/os-ii,” in 2010 Third International Conference on Intelligent
Networks and Intelligent Systems, pp. 177–180, 2010.
[11] L. Abeni and G. Buttazzo, “Integrating multimedia applications in hard real-time systems,” in
Proceedings 19th IEEE Real-Time Systems Symposium (Cat. No.98CB36279), pp. 4–13, 1998.
[12] Y. Matsubara, S. Honda, and H. Takada, “Hierarchical scheduling for integrating real-time
applications with interrupt routines,” in 2009 International SoC Design Conference (ISOCC),
pp. 384–387, 2009.
[13] L. Leyva-del-Foyo, P. Mejia-Alvarez, and D. de Niz, “Predictable interrupt scheduling with
low overhead for real-time kernels,” in 12th IEEE International Conference on Embedded and
Real-Time Computing Systems and Applications (RTCSA’06), pp. 385–394, 2006.

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