三維分佈奈米晶體與結晶化高介電材料應用於非揮發性記憶體之研究

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研究生：	張嘉軒 Chang, Chia-Hsuan
論文名稱：	三維分佈奈米晶體與結晶化高介電材料應用於非揮發性記憶體之研究 Study on Nanocrystals Three-Dimensionally Embedded in Trapping Layer and Crystallization of High-k Materials for Nonvolatile Memory
指導教授：	巫勇賢 Wu, Yung-Hsien
口試委員:
學位類別：	碩士 Master
系所名稱：	原子科學院 - 工程與系統科學系 Department of Engineering and System Science
論文出版年：	2009
畢業學年度：	97
語文別：	中文
論文頁數：	81
中文關鍵詞：	奈米晶體、非揮發性記憶體、高介電材料
外文關鍵詞：	nanocrystals, nonvolatile memory, high-k materials
相關次數：	點閱：3 下載：0
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近幾年來，奈米晶體 (nanocrystals, NCs) 被廣泛研究用於非揮發性記憶體上以克服傳統浮停閘 (floating gate, FG) 記憶體的微縮 (scaling) 限制。浮停閘記憶體在經過多次資料的讀寫過程後，穿隧氧化層 (tunnel oxide) 所產生的漏電路徑將會導致儲存單元中的電荷全部流失，而這個問題隨著尺寸微縮後會變得更嚴重，因此穿隧氧化層厚度將成為限制元件微縮的重要關鍵，若穿隧氧化層無法做薄，也無法降低操作電壓與提升讀寫速度。為了解決上述問題與提升元件的可靠度 (reliability)，具有分離式電荷儲存中心的SONOS (silicon-oxide-nitride-oxide-silicon) 記憶體與奈米晶體記憶體被提出來，並被認為很有潛力能夠改善傳統浮停閘記憶體的缺點，除此之外，同時結合了SONOS結構與奈米晶體結構的混合型 (hybrid) 記憶體也被研發出來。
由於混合型記憶體相較於單純的SONOS記憶體或單純的奈米晶體記憶體，有相對突出的特性表現，因此本論文的研究重點即在於如何形成混合型的結構。在本論文中，提出使用相分離 (spinodal phase segregation) 的方法來形成氮化鈦 (TiN) 的奈米晶體埋藏於氮化矽 (silicon nitride) 薄膜中，此種方法的特點在於氮化鈦是金屬奈米晶體、具有較高的功函數且本身熱穩定性夠高，製程上步驟簡單、所形成的奈米晶體呈現三維散亂分佈於氮化矽之中。本研究成功做出此結構且製作成記憶體來量測其特性，發現此元件可以操作在相當低的電壓，而同時也使用材料分析儀器來觀察奈米晶體的形成。
本論文的第二部份則是探討結晶化與否對高介電常數材料的儲存特性所造成之影響。本研究先以反應式磁控濺鍍系統沉積氮氧化鋯 (ZrON) 薄膜，再對其進行不同溫度的熱退火處理以產生不同的結晶狀態，並將之做成記憶體元件以量測其電性，同時也使用材料分析儀器觀察結晶狀態之形成。

摘要................................................................................................................................ i
誌謝............................................................................................................................... ii
總目錄.......................................................................................................................... iii
表目錄.......................................................................................................................... vi
圖目錄......................................................................................................................... vii

第一章  序論............................................................................................................... 1
1-1 前言........................................................................................................................ 1
1-2 半導體記憶體簡介................................................................................................ 2
1-3 半導體記憶體的重要特性.................................................................................... 3
1-3-1 寫入/抹除/讀取速度.................................................................................... 3
1-3-2 操作電壓...................................................................................................... 3
1-3-3 記憶窗口...................................................................................................... 4
1-3-4 資料保存度.................................................................................................. 4
1-3-5 耐用度.......................................................................................................... 4
1-4 論文架構............................................................................................................... 4
第二章  文獻回顧...................................................................................................... 7
2-1  Floating gate nonvolatile memory....................................................................... 7
   2-1-1 浮停閘記憶體之結構.................................................................................. 7
   2-1-2 浮停閘記憶體之操作原理.......................................................................... 7
2-2  SONOS nonvolatile memory............................................................................... 8
   2-2-1  SONOS記憶體結構.................................................................................. 8
   2-2-2  SONOS記憶體之操作原理...................................................................... 8
2-3  Nanocrystals nonvolatile memory..................................................................... 10
   2-3-1 奈米晶體記憶體之結構............................................................................ 10
   2-3-2 奈米晶體記憶體之操作原理.................................................................... 10
   2-3-3 金屬奈米晶體............................................................................................ 11
   2-3-4 奈米晶體的形成........................................................................................ 12
2-4  Hybrid nonvolatile memory............................................................................... 12
   2-4-1 混合型記憶體之結構................................................................................ 12
   2-4-2 混合型記憶體之操作原理........................................................................ 12
   2-4-3 雙層混合型結構........................................................................................ 13
2-5 未來趨勢與研究方向......................................................................................... 13
第三章  TiN-NCs混合型記憶體............................................................................ 34
3-1 實驗動機與目標................................................................................................. 34
   3-1-1 相分離........................................................................................................ 34
   3-1-2 使用氮化鈦作為奈米晶體........................................................................ 35
3-2 實驗製程流程步驟.............................................................................................. 35
   3-2-1 利用相分離形成氮化鈦奈米晶體埋藏於氮化矽內結構........................ 35
   3-2-2 完整步驟流程............................................................................................ 36
3-3 物性分析.............................................................................................................. 37
   3-3-1  X光繞射 (XRD) 分析........................................................................... 37
   3-3-2 穿透式電子顯微鏡 (TEM) 分析............................................................. 37
3-4 電性分析.............................................................................................................. 38
   3-4-1 量測儀器的建立........................................................................................ 38
   3-4-2 電容-電壓特性與磁滯量測....................................................................... 38
   3-4-3 寫入與抹除量測........................................................................................ 39
   3-4-4 耐用度量測................................................................................................ 39
   3-4-5 資料保存度量測........................................................................................ 39
第四章  二氧化鋯記憶體......................................................................................... 51
4-1 實驗動機與目標................................................................................................. 51
   4-1-1 形成氮化鋯 (ZrN) 與二氧化鋯 (ZrO2) 之結構.................................... 51
   4-1-2 使用氮化鋯作為奈米晶體........................................................................ 51
4-2 實驗製程流程步驟............................................................................................. 52
   4-2-1 使用反應式濺鍍形成氮氧化鋯................................................................ 52
   4-2-2 完整步驟流程............................................................................................ 52
4-3 物性分析............................................................................................................. 53
   4-3-1  X光繞射分析.......................................................................................... 53
   4-3-2  X光光電子譜儀 (XPS) 分析................................................................ 53
4-4 電性分析.............................................................................................................. 54
   4-4-1 電容-電壓特性與磁滯量測....................................................................... 54
   4-4-2 閘極漏電流量測........................................................................................ 55
   4-4-3 記憶窗口受頻率影響之量測.................................................................... 56
4-4-4 寫入與抹除量測........................................................................................ 57
   4-4-5 耐用度量測................................................................................................ 57
   4-4-6 資料保存度量測........................................................................................ 58
第五章  結論與未來展望......................................................................................... 73
參考文獻..................................................................................................................... 75

                                

[1] J. Bardeen and W. H. Brattain, “The Transistor, a Semiconductor Triode,” Phys. Rev., vol. 71, pp. 230-231, 1984.
[2] J. S. Kilby, “Invention of the Integrated Circuit,” IEEE Trans. Electron Devices, vol. ED-23, no. 7, pp. 648-654, 1976. U.S. Patent 3, 138, 743 (filed 1959, granted 1964).
[3] D. Kahng and S. M. Sze, “A Floating Gate and its Application to Memory Devices,” Bell Syst. Tech., vol. 46, pp. 1288, 1967.
[4] R.H. Dennard, United States Patent 3387286, July 14, 1967.
[5] H. A. R. Wegener, A. J. Lincoln, H. C. Pao, M. R. O’Connel, and R. E. Oleksiok, “Metal Insulator Semiconductor Transistors as a Nonvolatile Storage” IEDM Tech. Dig., abstract 59, 1967.
[6] M. N. Baibich, J. M. Broto, A. Fert, F. Nguyen Van Dau, F. Petroff, P. Etienne, G. Creuzet, A. Friederich, and J. Chazelas, “Giant Magnetoresistance of (001) Fe/(001)Cr Magnetic Superlattices,” Phys. Rev. Lett., vol. 61, no. 21, pp. 2472-2475, 1988.
[7] G. Binasch, P. Gr□nberg, F. Saurenbach, and W. Zinn, “Enhanced Magnetoresistance in Layered Magnetic Structures with Antiferromagnetic Interlayer Exchange,” Phys. Rev. B, vol. 39, no. 7, pp. 4828-4830, 1989.
[8] G. A. Prinz, “Magnetoelectronics,” Science, vol. 282, pp. 1660-1663, 1988.
[9] S. Lai and T. Lowrey “OUM - A 180 nm Nonvolatile Memory Cell Element Technology for Stand Alone and Embedded Applications,” IEDM Tech. Dig., pp. 803-806, 2005.
[10] E. Suzuki, H. Hayashi, K. Ishii, and Y. Hayashi, “A Low-Voltage Alterable EEPROM with Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) structures,” IEEE Trans. Electron Devices, vol. ED-30, no. 2, pp. 122-128, 1983.
[11] F. R. Libsch and M.H. White, “Charge Transport and Storage of Low Programming Voltage SONOS/MONOS Memory Devices,” Solid-State Electron., vol. 33, pp. 105-126, 1990.
[12] H. Reisinger, M. Franosch, B. Hasler, and T. Bohm, “A Novel SONOS Structure for Nonvolatile Memories with Improved Data Retention,” Symp. On VLSI Tech. Dig., 9A-2, pp. 113-114, 1997.
[13] M. K. Cho, and D. M. Kim, “High Performance SONOS Memory Cells Free of Drain Turn-On and Over-Erase: Compatibility Issue with Current Flash Technology,” IEEE Electron Device Lett., vol. 21, no. 8, pp. 399-401, 2000.
[14] I. Fijiwara, H. Aozasa, K. Nomoto, S. Tanaka, and T. Kobayashi, “High Speed Program/Erase sub 100nm MONOS Memory Cell,” Proc. 18th Non-Volatile Semiconductor Memory Workshop, pp. 75, 2001.
[15] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Lett., vol. 21, no. 11, pp. 543-545, 2000.
[16] T. Wang, W. J. Tsai, S. H. Gu, C. T. Chan, C. C. Yeh, N. K. Zous, T. C. Lu, S. Pan, and C. Y. Lu, “Reliability Models of Data Retention and Read-Disturb in 2-bit Nitride Storage Flash Memory Cells,” IEDM Tech. Dig., pp. 169-172, 2003.
[17] T. S. Chen, K. H. Wu, H. Chung, and C. H. Kao, “Performance Improvement of SONOS Memory by Bandgap Engineering of Charge-Trapping Layer,” IEEE Electron Device Lett., vol. 25, no. 4, pp. 205-207, 2004.
[18] H. T. Lue, S. Y. Wang, E. K. Lai, Y. H. Shih, S. C. Lai, L. W. Yang, K. C. Chen, J. Ku, K. Y. Hsieh, R. Liu, and C. Y. Lu, “BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability,” IEDM Tech. Dig., pp. 547-550, 2005.
[19] C. H. Lee, K. C. Park, and K. Kim, “Charge-Trapping Memory Cell of SiO2 /SiN/High-k Dielectric Al2O3 with TaN Metal Gate for Suppressing Backward-Tunneling Effect,” Appl. Phys. Lett., vol. 87, pp. 073510, 2005.
[20] Y. N. Tan, W. K. Chim, B. J. Cho, and W. K. Choi, “Over-Erase Phenomenon in SONOS-Type Flash Memory and its Minimization Using a Hafnium Oxide Charge Storage Layer,” IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1143-1147, 2004.
[21] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and D. Buchanan, “Volatile and Non-Volatile Memories in Silicon with Nano-Crystal Storage,” IEDM Tech. Dig., pp. 521-524, 1995.
[22] S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, “A Silicon Nanocrystals Based Memory,” Appl. Phys. Lett., vol. 68, no. 10, pp. 1377-1379, 1996.
[23] G. Puzzilli and F. Irrera, “Data Retention of Silicon Nanocrystal Storage Nodes Programmed with Short Voltage Pulses,” IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 775-781, 2006.
[24] Y. C. King, T. J. King, and C. Hu, “Charge-Trap Memory Device Fabricated by Oxidation of Si1-xGex,” IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 696-700, 2001.
[25] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal Nanocrystal Memories—Part I: Device Design and Fabrication,” IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1606-1613, 2002.
[26] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal Nanocrystal Memories—Part II: Electrical Characteristics,” IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1614-1622, 2002.
[27] C. Lee, J. Meteer, V. Narayanan, and E. C. Kan, “Self-Assembly of Metal Nanocrystals on Ultrathin Oxide for Nonvolatile Memory Applications,” J. Electronic Materials, vol. 34, no. 1, pp. 1-11, 2005.
[28] S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi, “Single Charge and Confinement effects in nano-crystal Memory,” Appl. Phys. Lett., vol. 69, no. 9, pp. 1232-1234, 1996.
[29] H. I. Hanafi, S. Tiwari, and I. Khan, “Fast and Long Retention-Time Nano-Crystal Memory,” IEEE Trans. Electron Devices, vol. 43, no. 9, pp. 1553-1558, 1996.
[30] Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, “Effects of Traps on Charge Storge Characteristics in Metal-Oxide-Semiconductor Memory Structures Based on Silicon Nanocrystals,” J. Appl. Phys., vol. 84, no. 4, pp. 2358, 1998.
[31] M. Saitoh, E. Nagata, and T. Hiramoto, “Large Memory Window and Long Charge-Retention Time in Ultranarrow Channel Silicon Floating-Dot Memory,” Appl. Phys. Lett., vol. 82, no. 11, pp. 1787-1789, 2003.
[32] E. Kapetanakis, P. Normand, and D. Tsoukalas, “Room Temperature Single-Electron Charging Phenomena in Large-Area Nanocrystal Memory Obtained by Low-Energy Ion Beam Synthesis,” Appl. Phys. Lett., vol. 80, no. 15, pp. 2794-2796, 2002.
[33] T. Ohzone, T. Matsuda, and T. Hori, “Erase/Write Cycle Test of n-MOSFET’s with Si-Implanted Gate-SiO2,” IEEE Trans. Electron Devices, vol. 43, no. 9, pp. 1374-1381, 1996.
[34] C. Lee, Z. Liu, and E. C. Kan, “Investigation on Process Dependence of Self-Assembled Metal Nanocrystals,” Mater. Res. Soc. Symp. Proc., 737, F8.18.1, 2003.
[35] W. K. Choi and W. K. Chim, “Observation of Memory Effect in Germanium Nanocrystals Embedded in an Amorphous Silicon Oxide Matrix of a Metal-Insulator-Semiconductor Structure,” Appl. Phys. Lett., vol. 80, no. 11, pp. 2014-2016, 2002.
[36] L. W. Teo, W. K. Choi, W. K. Chim, V. Ho, C. M.Moey, M. S. Tay, C. L. Heng, Y. Lei, D. A. Antoniadis, and E. A. Fitzgerald, “Size Control and Charge Storage Mechanism of Germanium Nanocrystals in a Metal-Insulator-Semiconductor Structure,” Appl. Phys. Lett., vol. 81, no. 19, pp. 3639-3641, 2002.
[37] V. Ho, L. W. Teo, W. K. Choi, W. K. Chim, and M. S. Tay, “Effect of Germanium Concentration and Tunnel Oxide Thickness on Nanocrystal Formation and Charge Storage/Retention Characteristics of a Trilayer Memory Structure,” Appl. Phys. Lett., vol. 83, no. 17, pp. 3558-3560, 2003.
[38] S. Veprek, S. Reiprich, and Li Shizhi, “Superhard Nanocrystalline Composite Materials: The TiN/Si3N4 System,” Appl. Phys. Lett., vol. 66, no. 20, pp. 2640-2642, 1995.
[39] S. Veprek and S. Reiprich, “A Concept for The Design of Novel Superhard Coatings,” Thin Solids Films, vol. 268, pp. 64-71, 1995.
[40] P. Nesladek and S. Veprek, “Superhard Nanocrystalline Composites with Hardness of Diamond,” Phys. Stat. Sol. (a), vol. 177, pp. 53-62, 2000.
[41] S. Coffa, “Light From Silicon,” IEEE Spectrum, pp. 44-49, 2005.
[42] R. A. Rao, R. F. Steimle, M. Sadd, C. T. Swift, B. Hradsky, S. Straub, T. Merchant, M. Stoker, S. G. H. Anderson, M. Rossow, J. Yater, B. Acred, K. Harber, E. J. Prinz, B. E. White Jr., and R. Muralidhar, “Silicon Nanocrystal Based Memory Devices for NVM and DRAM Applications,” Solid-State Electronics, vol. 48, pp. 1463-1473, 2004.
[43] R. F. Steimle, M. Sadd, R. Muralidhar, R. Rao, B. Hradsky, S. Straub, and B. E. White Jr, “Hybrid Silicon Nanocrystal Silicon Nitride Dynamic Random Access Memory,” IEEE Trans. Nanotechnology, vol. 2, pp. 335-340, 2003.
[44] C. Lee, T. H. Hou, and E. C. C. Kan, “Nonvolatile Memory with a Metal Nanocrystal/Nitride Heterogeneous Floating-Gate,” IEEE Trans. Electron Devices, vol. 52, pp. 2697-2702, 2005.
[45] S. Veprek, M. G. J. Veprek-Heijman, P. Karvankova and J. Prochazka, “Different Approaches to Superhard Coatings and Nanocomposites,” Thin Solid Film, vol. 476, pp. 1-29, 2005.
[46] R. F. Zhang and S. Veprek, “On the Spinodal Nature of the Phase Segregation and Formation of Stable Nanostructure in the Ti–Si–N system,” Materials Science and Engineering A, vol. 424, pp. 128-137, 2006.
[47] S. Choi, S.-S. Kim, M. Chang, H. Hwang, S. Jeon and C. Kim, “Highly Thermally Stable TiN Nanocrystals as Charge Trapping Sites for Nonvolatile Memory Device Applications,” Appl. Phys. Lett., vol. 86, pp. 123110, 2005.
[48] H. C. Barshilia, B. Deepthi, A. S. Arun Prabhu, and K. S. Rajam, “Superhard Nanocomposite Coatings of TiN/Si3N4 Prepared by Reactive Direct Current Unbalanced Magnetron Sputtering,” Surf. Coat. Technol., vol. 201, pp. 329-337, 2006.
[49] P. Normand, E. Kapetanakis, P. Dimitrakis, D. Tsoukalas, K. Beltsios, N. Cherkashin, C. Bonafos, G. Benassayag, H. Coffin, A. Claverie, V. Soncini, A. Agarwal and M. Ameen, “Effect of Annealing Environment on the Memory Properties of Thin Oxides with Embedded Si Nanocrystals Obtained by Low-Energy Ion-Beam Synthesis,” Appl. Phys. Lett., vol. 83, no. 1, pp. 168-170, 2003.
[50] L. Cunha, F. Vaz, C. Moura, L. Rebouta, P. Carvalho, E. Alves, A. Cavaleiro, Ph. Goudeau, and J. P. Riviere, “Structural Evolution in ZrNxOy Thin Films as a Function of Temperature,” Surf. Coat. Technol., vol. 200, pp. 2917-2922, 2006.
[51] Y. Gotoh, K. Kagamimori, H. Tsuji, and J. Ishikawa, “Ion Beam Assisted Deposition of Tantalum Nitride Thin Films for Vacuum Microelectronics Devices,” Surf. Coat. Technol., vol. 158-159, pp. 729-731, 2006.
[52] I. Milosev, H. H. Strehblow, M. Gaberscek, and B. Navinsek, “Electrochemical Oxidation of ZrN Hard (PVD) Coatings Studied by XPS,” Surface and Interface Analysis, vol. 24, pp. 448-458, 1996.
[53] I. Milosev, H. H. Strehblow, and B. Navinsek, “Comparison of TiN, ZrN and CrN Hard Nitride Coatings: Electrochemical and Thermal Oxidation,” Thin Solid Films, vol. 303, pp. 246-254, 1997.
[54] M. Koyama, K. Suguro, M. Yoshiki, Y. Kamimuta, M. Koike, M. Ohse, C. Hongo, and A. Nishiyama, “Thermally Stable Ultra-Thin Nitrogen Incorporated ZrO2 Gate Dielectric Prepared by Low Temperature Oxidation of ZrN,” IEDM Tech. Dig., pp. 459-462, 2001.
[55] J. C. Wang, S. H. Chiao, C. L. Lee, T. F. Lei, Y. M. Lin, M. F. Wang, S. C. Chen, C. H. Yu, and M. S. Liang, “A Physical Model for the Hysteresis Phenomenon of the Ultrathin ZrO2 Film,” J. Appl. Phys., vol. 92, no. 7, pp. 3936-3940, 2002.
[56] C. L. Heng and T.G. Finstad, “Electrical Characteristics of a Metal–Insulator–Semiconductor Memory Structure Containing Ge Nanocrystals,” Physica E, vol. 26, pp. 386-390, 2005.
[57] B. Euzent, N. Boruta, J. Lee, and C. Jenq, “Reliability Aspects of A Floating Gate EEPROM,” Proc. Int. Reliability Phys. Symp., pp. 11-16, 1981.

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