連結標準基本單元功率特性之精確暫存器轉換層級的功率測量

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研究生：	張凱翔 Kai-Shuang Chang
論文名稱：	連結標準基本單元功率特性之精確暫存器轉換層級的功率測量 Accurate RTL Power Estimation Linked with Standard Cell Power Characterization
指導教授：	黃錫瑜 Shi-Yu Huang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	46
中文關鍵詞：	功率估測、暫存器轉移階層
外文關鍵詞：	power estimation, RTL
相關次數：	點閱：3 下載：0
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近年來，隨著半導體製程進步，積體電路的規模不斷成長，使得功率消耗過大，導致電路過熱，連帶電路的效能大打折扣，所以功率消耗成為大家注重的課題。為了要處理今日愈漸複雜的晶片密度，在電路設計階段中，如果可以愈早知道電路的功率消耗，愈能在早期幫助設計者做功率上的最佳化設計，因此，一個正確快速地功率估計方法就變得舉足輕重。
我們在論文中提到透過每個基本單元(cell)的功率特性，將它與暫存器轉移階段的評估功率軟體做連結，如此一來不但可以擁有高階層次評估的速度，也兼具低階模擬器的精確度。所提出的測量演算法不僅是考慮短暫的時脈衝波(glitch)，還有每個單元的輸出電容大小，依據所建立的功率模型主要分為組合電路部分的全電壓擺幅也包括了部分的電壓擺幅的模型。另外，針對循序電路部分的觸發器(flip-flop)，我們將之分為輸入級的功耗和輸出級的功耗兩種行為，更精確地描繪出來它的功耗。建立好的功率特徵被存放在資料庫內，當我們與過去暫存器的功率估測軟體連結後，建立功率模型階段再引入這些基本單元相對應的功率值，便達成一個擁有低階功率模擬器精確度的強力工具。
實驗的結果發現，這樣的功率測量模型，能夠得到準確的功率消耗，在測試的基準電路，得到的平均誤差大約是2%以內。

We investigate in the thesis the cell-based power characterization and its linkage to an RTL (Register Transfer Level) power estimation flow for CMOS logic circuits. The proposed power characterization method is highly accurate because of taking into account the effects of glitches, output loading, and logic state transition in registers. For each combinational cell, we build the power models for full swings as well as for partial swings. For flip-flop cells, we propose a split model that treats the input stage and output stage separately to increase its accuracy. Experimental results on a number of real-life test cases show that the estimation error can be kept within 2% error on the average as compared to that obtained by pure Nanosim simulation.

Introduction                                                     7
1 Motivation……...…………….……………………………………………....8
2 Organization…………………………………………………………….…...13
Preliminaries                                                    14
1 Power consumption components…………………………………….……...14
1.1 Static power consumption…………………………………….………14
1.2 Dynamic power consumption………………………………….……...16
2 Power estimation techniques…………….………………………….…….....18
2.1 System-level…………………………………………………………..18
2.2 RTL-level………………………………………………………….…..19
2.3 Gate-level…………………………………...........................................20
2.4 Transistor-level…………………………………………………….….21
Cell Characterization and Model for Partial Swing                    22
1 Standard cell characterization……………………………………………….22
2 Partial swing model………………………………………………………… 26
3 Link with previous work………………….....................................................29
Implementation                                                  31
1 System overview…………………………………………………………….32
1.1 Data preparation………………………………………………………..34
1.2 Power modeling phase…………………………………………………35
1.3 Power extrapolation phase……………………………………………..37
2 Extended with ASIC design flow…………………………………………….37
Experimental Results                                              39
1 Usage of our tool……………………………………………….………….....39
2 Experiments………………………………………………….……………....41
2.1 The large case in benchmark………...…………………….………..….41
2.2 The effect of glitch model…………………………………...…………43
2.3 The effect of split model…………………………………….…………43
3 The overall comparison…………………………………………….…….......44
Conclusion                                                      46
Acknowledgements                                                 47
Bibliography                                                      47

                                

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