研究生: |
李德量 Lee, Te Liang |
---|---|
論文名稱: |
內建差動讀取的非揮發性記憶體元件研究 The Study of CMOS Logic Based Nonvolatile Memory Cells with Built-in Differential Read Operation |
指導教授: |
林崇榮
Lin, Chrong Jung 金雅琴 King, Ya-Chin |
口試委員: |
連振炘
Lien, Chen-Hsin 張彌彰 Chang, Mi-Chang 陳 新 Chen, Hsin 金雅琴 King, Ya-Chin 林崇榮 Lin, Chrong Jung 莊紹勳 Chung, Steve S. 吳自康 Wu, Ken |
學位類別: |
博士 Doctor |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2013 |
畢業學年度: | 101 |
語文別: | 英文 |
論文頁數: | 146 |
中文關鍵詞: | 非揮發性記憶體 、差動讀取 、自我修復能力 、邏輯製程相容 、嵌入式系統單晶片 |
外文關鍵詞: | Nonvolatile Memory, Differential Read, Self-recovery, Logic Process Compatible, Embedded SOC System |
相關次數: | 點閱:3 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
本論文提出三種可應用於嵌入式系統單晶片的新式差動讀取之非揮發性記憶體元件。所提出的新式差動讀取之非揮發性記憶體元件以完全邏輯製程相容或既有的非揮發性記憶體技術製作,故可維持與現行業界非揮發性記憶體解決方案的可行性及效能。同時,藉由其差動讀取的雙倍window以提昇浮動閘極非揮發性記憶體的資料保存能力。另外,除了可相容於邏輯製程之非揮發性記憶體元件,可相容於邏輯製程之高壓元件也被提出,進而達成完全邏輯製程相容之嵌入式系統的非揮發性記憶體模組。
首先,本論文討論兩種邏輯製程相容的新型差動式多次性可編程非揮發性記憶體。接著,為實現完全邏輯製程相容的嵌入式系統之非揮發性記憶體模組,本文也討論一個可完全相容於邏輯製程之高壓接點閘極金氧半場效電晶體。
此外,我們也提出一種新型差動式同時具有自我修復能力的分離式閘極快閃記憶體。由於,分離式閘極快閃記憶體的快速編程、抹除的能力已被驗證,利用差動式讀取及其自我修復能力更提昇其資料保存能力,使之可運用於高可靠性需求的產品。
總結,本文提出數種可基於原有非揮發性記憶體架構及製程,提昇非揮發性記憶體資料保存能力的解決方案。這些解決方案可保留已驗證非揮發性記憶體元件之優勢,不需額外的製程調整及控制,便可運用於更高可靠性需求的產品應用之上。
This dissertation proposes three types of new novel differential nonvolatile memory (NVM) cells for advanced embedded system on a chip (SOC) applications. The novel NVM cells with differential read function were fabricated by fully complementary metal–oxide–semiconductor (CMOS) logic compatible processes or existing NVM technologies, so that their feasibility and performance are comparable to the current industrial NVM solutions. Moreover, the floating gate (FG) data retention performance can be enhanced by the differential read operation, which has a double read window. Further, in addition to the logic-compatible NVM cells, a logic-compatible high voltage device which can realize a fully logic-compatible NVM module for embedded systems was also proposed.
First, two fully logic-compatible multiple-time programmable (MTP) floating gate NVM cells with differential read operations are proposed. Then, in order to realize a fully logic-compatible NVM module for embedded systems, a high voltage contact gate metal–oxide–semiconductor field-effect transistor (MOSFET) with fully logic-compatible process was also proposed.
In addition, a new high-density differential split-gate flash memory cell with self-recovery function is proposed. Since the cell process and tip erase structure are totally inherited from the proven split-gate flash technology, the highly efficient program and erase performances are retained in the new cell. However, data retention and endurance capability are much improved by the new built-in self-recovery function with differential read operation.
In summary, several data retention performance enhancement solutions based on existing proven NVM cell structures are discussed in this dissertation. These solutions, which maintain the advantages of original NVM cells, can be directly used for high reliability requirement products without any special process tuning or control.
[1] Heath, Steve, "Embedded systems design," EDN series for design engineers (2 ed.). Newnes. p. 2. ISBN 978-0-7506-5546-0.
[2] H. Hidaka, "Value creation and technological convergence by evolution of embedded non-volatile memory," in MTDT, 2007, pp. 13-14.
[3] S. Bhattacharya, K. Lai, K. Fox, P. Chan, E. Worley, U. Sharma, Liming Hwang, and G. P. Li, "Improved performance and reliability of split gate source-side injected flash memory cells," in IEDM, 1996, pp. 339-342.
[4] C. J. Huang, and Y. C. Liu, "A scalable novel P-channel nonvolatile memory cell," in NVMT, 2005, pp. 11-14.
[5] K. Huang, Y. K. Fang, D. N. Yaung, D.Kuo, C. S. Wang, and M. S. Liang, "Improved programming performance of EEPROM/flash cell using post-poly-Si gate N/sub 2/O annealing," IEEE Electronics Lett., vol. 35, pp. 1112-1114, 1999.
[6] X. Liu, V. Markov, A. Kotov, T. N. Dang, A. Levi, I. Yue, A. Wang, and R. Qian, "Endurance characteristics of superflash memory," in ICSICT, 2006, pp. 763-765.
[7] B. Chen, "Highly reliable superflash embedded memory scaling for low power SoC," in VLSI-TSA, 2007, pp. 1-2.
[8] V. Markov, K. Korablev, A. Kotov, X. Liu, Y. B. Jia, T. N. Dang, and A. Levi, "Charge-gain program disturb mechanism in split-gate flash memory cell," in IRW, 2007, pp. 43-47.
[9] Y. S. Chu, Y. H. Wang, C. Y. Wang, Y. H. Lee, A. C. Kang, R. Ranjan, W. T. Chu, T. C. Ong, H. W. Chin, and K. Wu, "Split-gate flash memory for automotive embedded applications," in IRPS, 2011, pp. 636-640.
[10] Y. H. Wang, Y. S. Tsair, A. C. Kang, W. T. Chu, E. Chen, J. R. Shih, H. W. Chin, and K. Wu, "Split-gate flash memory for automotive embedded applications," in RELPHY, 2007, pp. 558-563.
[11] C. S. Bill, S. Kaza, W. D. Cai, T.-n. Fang, D. Gaun, E. Gershon, M. A. Van Buskirk, and J. Wu, "Use of periodic refresh in medium retention memory arrays," U. S. Patent No. 7,474,579, 2009.
[12] S. M. Sze, Physics of Semiconductor Devices, 2nd Edition, John Wiley & Sons, Inc., 1985.
[13] Fowler R. H. and Nordheim L., "Electron Emission in Intense Electric Fields," Proceedings of the Royal Society of London, vol. A119, pp. 173-81, 1928.
[14] M. Lenzlinger and E.H. Snow, "Fowler-Nordheim Tunneling into Thermally Grown SiO2," J. Appl. Phys., Vol. 40, p. 278, 1969.
[15] P. E. Cottrell, R. R. Troutman, and T. H. Ning, "Hot Electron Emission in n-Channel IGFET’s," IEEE J. Solid State Circuits, vol. SC-14, p.442,1979.
[16] C. Hu, "Lucky-electron model of channel hot electron emission," IEEE IEDM Tech. Dig., pp. 22-25, 1979.
[17] T. C. Ong, A. Fazio, N. Mielke, S. Pan, N. Tighos, G. Atwood, and S. Lai, "Erratic erase in ETOXTM Flash Memory Array," Symp. VLSI Tech. Dig., p.83, 1993.
[18] T. C. Ong, K. Seki, P. K. Ko, and C. Hu, "p-MOSFET gate current and device degradation," Symp. Reliability Physics, pp.178-182, 1989.
[19] K. Yoshikawa, M. Sato, and Y. Ohshima, "A Reliable Profiled Lightly Doped Drain (PLD) Cellfor High-Density Submicrometer EPROM’s andFlash EEPROM’s," IEEE Trans. on Electron Devices, vol. ED-37, no. 4, pp. 999-1006, Apr. 1990.
[20] T. Ohnakado, K. Mitsunaga, and M. Nunoshita, "Novel Electron Injection Method Using Band- to-Band TunnelingInduced Hot Electron(BBHE) for Flash Memory with a P-channel Cell," IEEE IEDM Tech. Dig., pp. 279-282, 1995.
[21] T. Ohnakado, H. Onoda, O. Sakamoto, K. Hayashi, N. Nishioka, H. Takada, K. Sugahara, N. Ajika, and S. Satoh, "Device Characteristics of 0.35um P-Channel DINOR Flash Memory Using Band-to-Band Tunneling-Induced Hot Electron (BBHE) Programming," IEEE Trans. on Electron Devices, vol. 46, no. 9, Sept. 1999.
[22] L. R. Carley, "Trimming analog circuits using floating-gate analog MOS memory," IEEE J. Solid-State Circuits, vol. 24, no. 6, 1989, pp. 1569-1575.
[23] R. J. McPartland, et al., "1.25 volt, low cost, embedded flash memory for low density applications," in Sympposium on VLSI Circuits Digest of Technical Papers, 2000, pp. 158-161.
[24] R. Barsatan, et al., "A Zero-Mask One-Time Programmable Memory Array for RFID Applications," in Proc. ISCAS, 2006, pp. 975-978.
[25] K. Ohsaki, N. Asamoto, and S. Takagaki, "A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes," IEEE Journal of Solid State Circuit, vol. 29, no. 3, pp. 311-316, Mar.1994.
[26] K. Ohsaki, R. Cho, and K. Shigaken, "EEPROM and Logic LSI Chip Including Such EEPROM," US patent 5465231, 1995.
[27] R.S.C. Wang, R.S.J. Shen, C.C.H. Hsu, "Neobit® - high reliable logic non-volatile memory (NVM)," in IPFA, 2004, pp. 111-114.
[28] ITRS, "Process Integration, Devices, and Structures," in International Technology Roadmap for Semiconductors, 2007 ed, 2007.
[29] Y.-C. King, T.-J. King, and C. Hu, "A long-refresh dynamic/quasi-nonvolatile memory device with 2-nm tunneling oxide," Electron Device Letters, IEEE, vol. 20, pp. 409-411, 1999.
[30] E. F. Runnion, S. M. I. Gladstone, R. S. Scott, D. J. Dumin, L. Lie, and J. Mitros, "Limitations on oxide thicknesses in flash EEPROM applications," in Reliability Physics Symposium, 1996. 34th Annual Proceedings., IEEE International, 1996, pp. 93-99.
[31] H. M. Lee, S. T. Woo, H. M. Chen, R. Shen, C. D. Wang, L. C. Hsia, and C. C. H. Hsu, "NeoFlash - True Logic Single Poly Flash Memory Technology," in Proc. 21st IEEE NVSMW, 2006, pp. 15-16.
[32] Y. Ma, T. Gilliland, B. Wang, R. Paulsen, A. Pesavento, C. H. Wang, H. Nguyen, T. Humes, and C. Diorio, "Reliability of pFET EEPROM with 70Å tunnel oxide manufactured in generic logic CMOS Processes," IEEE Trans. Device Mater. Rel., vol. 4, pp. 353-358, 2004.
[33] A. Pesavento, J. B. Frederic, and J. D. Hyde, "pFET nonvolatile memory," U.S. Patent No. 7,221,596, 2007.
[34] B. Wang, H. Nguyen, Y. Ma, and R. Paulsen, "Highly Reliable 90-nm Logic Multitime Programmable NVM Cells Using Novel Work-Function-Engineered Tunneling Devices," IEEE Trans. Electron Devices, vol. 54, pp. 2526-2530, 2007.
[35] B. Wang, M. Niset, Y. Ma, H. Nguyen, and R. Paulsen, "Scaling tunneling oxide to 50Å in floating-gate logic NVM at 65nm and beyond," in IEEE Int. Integrated Reliability Workshop Final Report, 2007, pp. 48-51.
[36] B. Wang and Y. Ma, "Opportunities and Challenges in Multi-Times-Programmable Floating-Gate Logic Non-Volatile Memories," in Int. Conf. NVSMW/ICMTD Joint, 2008, pp. 22-25.
[37] T. Horiuchi, "Storage and recovery of data based on change in MIS transistor characteristics," U.S. Patent No. 7,149,104, 2006.
[38] K. Noda, "Nonvolatile memory utilizing asymmetric characteristics of hot-carrier effect," U.S. Patent No. 7,321,505, 2008.
[39] J. V. Houdt, G. Groeseneken, and H. E. Maes, "An analytical model for the optimization of source-side injection flash EEPROM devices, " IEEE Trans. Electron Devices, vol. 42, pp. 1314-1320, 1995.
[40] Y. Ma, C. S. Pang, J. Pathak, S. C. Tsao, and C. F. Chang, "A novel highdensity contactless flash memory array using split-gate sources-side-injection cell for 5 V-only applications," in 1994 Symp. VLSI Technology Dig. Tech. Papers, vol. 5A, pp. 49-50.
[41] K. Chang, W. Chen, C. Swift, J. M. Higman, W. M. Paulson, and K. Chang, "A new SONOS memory using source-side injection for programming," IEEE Electron Device Lett., vol. 19, pp. 253-255, 1998.
[42] A. T. Wu, T. –Y. Chan, P. –K. Ko, and C. Hu, "A novel high-speed, 5-volt programming EPROM structure with source-side injection programming," in IEDM Tech. Dig., 1986, pp. 584-587.
[43] H. Guan, D. Lee, and G. P. Li, "An analytical model for optimization of programming efficiency and uniformity of split gate source-side injection SuperFlash memory," IEEE Trans. Electron Devices, vol. 50, pp. 809-815, 2003.
[44] S. Kianian, A. Levi, D. Lee, and Y.-W. Hu, "A Novel 3 Volts-Only, Small Sector Erase, High Density Flash E2PROM," in 1994 Symp. VLSI Technology Dig. Tech. Papers, pp. 71-72.
[45] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, "Introduction to Flash Memory," Proceeding of the IEEE, vol. 91, no. 4, April 2003, pp. 489-502.
[46] P. Cappelletti, R. Bez, D. Cantarelli, and L. Fratin, "Failure mechanisms of Flash cell in program/erase cycling," in IEDM Tech. Dig., 1994, pp. 291–294.
[47] S. Lai, "Flash memories: Where we were and where we are going," in IEDM Tech. Dig., 1998, pp. 971-973.
[48] K. Naruke, S. Taguchi, and M. Wada, "Stress-induced leakage current limiting to scale down EEPROM tunnel oxide thickness," in IEDM Tech. Dig., 1988, pp. 424-427.
[49] P. Olivio, T. N. Nguyen, and B. Ricco, "High-field-induced degradation in ultra-thin SiO2 films," IEEE Trans. Electron Devices, vol. 35, no. 12, pp. 2259-2267, Dec. 1988.
[50] R. Moazzami and C. Hu, "Stress-induced current in thin silicon oxide films," in IEDM Tech. Dig., 1992, pp. 139-142.
[51] D. Ielmini, A. S. Spinelli, and A. L. Lacaita, "Recent developments on Flash memory reliability," Microelectron. Eng., vol. 80, no. 1, pp. 321-328, Jun. 2005.
[52] Chad A. Lindhorst, Christopher J. Diorio, Troy N. Gilliland, Alberto Pesavento, Shail Srinivas, Yanjun Ma, Terry Hass, and Kambiz Rahimi, " Differential floating gate nonvolatile memories," U. S. Patent No. 6,950,342, 2005.
[53] K.-H. Lee and Y.-C. King, "New single-poly EEPROM with cell size down to 8F2 for high density embedded nonvolatile memory applications," in VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on, 2003, pp. 93-94.
[54] C.-H. Hsu, Y.-T. Lin, C.-H. Chu, S.-J. Shen, C.-S. Yang, and M.-C. Ho, "Electrically erasable programmable logic device," U.S. Patent No. 6,617,637, 2003.
[55] J. Peng, G. Rosendale, M. Fliesler, D. Fong, J. Wang, C. Ng, Z. S. Liu, and H. Luan, "A Novel Embedded OTP NVM Using Standard Foundry CMOS Logic Technology," in Non-Volatile Semiconductor Memory Workshop, 2006. IEEE NVSMW 2006. 21st, 2006, pp. 24-26.
[56] H.-K. Cha, I. Yun, J. Kim, B.-C. So, K. Chun, I. Nam, and K. Lee, "A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller," Solid-State Circuits, IEEE Journal of, vol. 41, pp. 2115-2124, 2006.
[57] Y.-H. Tsai, H.-M. Chen, H.-Y. Chiu, H.-S. Shih, H.-C. Lai, Y.-C. King, and C. J. Lin, "45nm Gateless Anti-Fuse Cell with CMOS Fully Compatible Process," in Electron Devices Meeting, 2007. IEDM 2007. IEEE International, 2007, pp. 95-98.
[58] M. Chen, C.-E. Huang, Y.-H. Tseng, Y.-C. King, and C.-J. Lin, "A New Antifuse Cell With Programmable Contact for Advance CMOS Logic Circuits," Electron Device Letters, IEEE, vol. 29, pp. 522-524, 2008.
[59] C.-E. Huang, H.-M. Chen, H.-C. Lai, Y.-J. Chen, Y.-C. King, and C. J. Lin, "A New Self-Aligned Nitride MTP Cell with 45nm CMOS Fully Compatible Process," in Electron Devices Meeting, 2007. IEDM 2007. IEEE International, 2007, pp. 91-94.
[60] F. R. L. Lin, W. Yen-Sen, and C. C. H. Hsu, "Multi-level p-channel flash memory," in Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on, 1998, pp. 457-463.
[61] B. Murari, F. Bertotti, and G. A. Vignola, "Smart Power ICs,".
[62] A. Yoo, Y. Onish, E. Xu, and W. T. Ng, "A Low-Voltage Lateral SJ-FINFET With Deep-Trench p-Drift Region," IEEE Electron Device Lett., vol.30, pp. 858-860, 2009.
[63] L. Guan, J. K. O. Sin, Z. Xiong, and H. Liu, "A Novel Drift Region Self-Aligned SOI Power MOSFET Using a Partial Exposure Technique," Proc. Intl. Symp. Power Semiconductor Devices & Integrated Circuits, pp. 159-162. 2005.
[64] J. C. W. Ng, J. K. O. Sin and L. Guan, "A Novel Sub-20V Power MOSFET with Improved On-Resistance and Threshold Variation," Proc. Intl. Symp. Power Semiconductor Devices & Integrated Circuits, pp. 91-94. 2008.
[65] C. Wang, H. Kan, F. Cen, Y. Yu, "Low-FOM planar MOSFET," in ICIMA, pp. 460-463. 2010.
[66] B. Zhang, W. Wang, W. Chen, Z. Li, and Z. Li, "High-Voltage LDMOS With Charge-Balanced Surface Low On-Resistance Path Layer," IEEE Electron Device Lett., vol.30, pp. 849-851, 2009.
[67] S. Xu, J. Korec, D. Jauregui, C. Kocon, S. Molly, H. Lin, G. Daum, S. Perelli, K. Barry, C. Pearce, O. Lopez, J. Herbsommer, "NexFET A New Power Device," Electron Devices Meeting (IEDM), pp. 145-148, 2009.
[68] J. C. W. Ng, J. K. O. Sin and L. Guan, "A Novel Planar Power MOSFET with Laterally Uniform Body and Ion-Implanted JFET Region," IEEE Electron Device Lett., vol. 29, no. 4, 2008.
[69] S. Matsumoto, Y. Hiraoka, and T. Sakai, "A High-Efficiency Thin-Film SOI Power MOSFET Having a Self-Aligned Offset Gate Structure for Multi-Gigahertz Applications," IEEE Trans. on Electron Devices, vol. 48, no. 6, pp. 1270-1274, 2001.
[70] W. Chen, B. Zhang, and Z. Li, "SJ-LDMOS with high breakdown voltage and ultra-low on-resistance," Electron. Lett., vol. 42, no. 22, pp. 1314–1316, 2006.
[71] S. Xu, Schnecksville. "Power LDMOS Transistor". [P] US patent 7,282,765 B2.2007
[72] B. J. Baliga, "Power Semiconductor Devices".
[73] T. Kobayashi, H. Abe, Y. Niimura, T. Yamada, A. Kurosaki, T. Hosen, and T. Fujihira, "High-Voltage Power MOSFETs Reached Almost to the Silicon Limit," Proc. Intl. Symp. Power Semiconductor Devices & Integrated Circuits, pp. 435-438. 2001.