由於半導體製程的微小化，晶片可靠度（reliability）的議題逐漸被重視。在晶片可靠度的議題中，晶片老化（aging）現象是造成晶片效能降低的最主要因素。一般來說，會使用即時監測（run-time monitoring）的方法來監控及計算老化效應帶來的影響，並且做晶片錯誤預測（chip failure prediction），在錯誤發生前提供警告。然而，這類的方法的最終目標是為了減緩老化的幅度，通常只會監控並預測電路上的延遲退化程度（delay degradation），並不會提供使用者有關任何晶片健康狀況的資訊。
在本論文中，我們提出一個晶片健康狀況預測方法，並且能夠考量到老化效應、製程、電壓、和溫度變化（PVT variations），以及工作負載（workload）的影響。使用者能夠透過我們預測的晶片健康狀況以及晶片年齡，來判斷晶片是否會在短期內發生錯誤。而我們提出的晶片健康狀況預測方法主要是透過一個新穎的監測策略，來追蹤具有代表性的受老化影響的延遲行為，而這些被觀測的延遲行為會成為機器學習方法用來預測受測晶片年齡的依據。實驗結果顯示，搭配我們提出的監測延遲的策略，跟蒙地卡羅模擬（Monte Carlo Simulation）的結果相比，我們用來預測晶片年齡的模型可以達到97.12% 的準確度，並且只需花費平均4.62% 的額外面積。在即時監測及預測晶片錯誤的領域當中，我們是第一個提出預測晶片年齡及提供即時晶片健康狀況的研究。

Reliability concerns of a chip are worsening due to the downscaling technology. Among the reliability issues, aging effect is the dominant concern since it degrades the circuit performance over time. Traditionally, run-time monitoring approaches are proposed to estimate aging effects. However, such techniques tend to predict and monitor delay degradation status for circuit mitigation measures rather than the chip health condition. In this paper, we propose an aging-aware chip health prediction methodology which adapts to PVT (Process, supply Voltage, and Temperature) variations and workload conditions. Our prediction methodology adopts an innovative on-chip delay monitoring strategy by tracing representative aging-aware delay behavior. The delay behavior is then fed into a machine learning engine to predict the age of a tested chip. Experimental results show that our strategy can obtain 97.12% accuracy with 4.62% area overhead on average compared with Monte Carlo simulation. To the best of the authors’ knowledge, this is the first work that accurately predicts current chip age and provides future chip health information.

[1] W. Wang, S. Yang, S. Bhardwaj, S. Vrudhula, F. Liu and Y. Cao, "The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 2, pp. 173-183, Feb. 2010.
[2] B. C. Paul, Kunhyuk Kang, H. Kufluoglu, M. A. Alam and K. Roy, "Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits," Proceedings of the Design Automation & Test in Europe Conference, Munich, 2006, pp. 1-6.
[3] M. Agarwal, B. C. Paul, M. Zhang and S. Mitra, "Circuit Failure Prediction and Its Application to Transistor Aging," 25th IEEE VLSI Test Symposium (VTS'07), Berkeley, CA, 2007, pp. 277-286.
[4] M.A. Alam, S. Mahapatra, “A comprehensive model of PMOS NBTI degradation,” Microelectronics Reliability, 45:71-81, 2005
[5] E. Mintarno et al., "Optimized self-tuning for circuit aging," 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, pp. 586-591.
[6] Vijayan; A. Koneru; S. Kiamehr; K. Chakrabarty; M. B. Tahoori, "Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring of Run-Time Stress," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol.PP, no.99, pp.1-1
[7] J. W. McPherson, "Reliability challenges for 45nm and beyond," 2006 43rd ACM/IEEE Design Automation Conference, San Francisco, CA, 2006, pp. 176-181.
[8] G. Yan, Y. Han and X. Li, "A unified online Fault Detection scheme via checking of Stability Violation," 2009 Design, Automation & Test in Europe Conference & Exhibition, Nice, 2009, pp. 496-501.
[9] G. Yan, Y. Han and X. Li, "SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 9, pp. 1627-1640, Sept. 2011.
[10] H. Dadgour and K. Banerjee, "Aging-resilient design of pipelined architectures using novel detection and correction circuits," 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, pp. 244-249.
[11] X. Wang, M. Tehranipoor, S. George, D. Tran and L. Winemberg, "Design and Analysis of a Delay Sensor Applicable to Process/Environmental Variations and Aging Measurements," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 8, pp. 1405-1418, Aug. 2012.
[12] J. Keane, T. H. Kim and C. H. Kim, "An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 6, pp. 947-956, June 2010.
[13] M. Wirnshofer, L. Heiß, G. Georgakos and D. Schmitt-Landsiedel, "An energy-efficient supply voltage scheme using in-situ Pre-Error detection for on-the-fly voltage adaptation to PVT variations," 2011 International Symposium on Integrated Circuits, Singapore, 2011, pp. 94-97.
[14] A. Amouri and M. Tahoori, "A Low-Cost Sensor for Aging and Late Transitions Detection in Modern FPGAs," 2011 21st International Conference on Field Programmable Logic and Applications, Chania, 2011, pp. 329-335.
[15] J. C. Vazquez, V. Champac, I. C. Teixeira, M. B. Santos and J. P. Teixeira, "Programmable aging sensor for automotive safety-critical applications," 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, pp. 618-621.
[16] R. Baranowski, F. Firouzi, S. Kiamehr, C. Liu, M. Tahoori and H. J. Wunderlich, "On-line prediction of NBTI-induced aging rates," 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, 2015, pp. 589-592.
[17] Cortes, Corinna, and Vladimir Vapnik. "Support-vector networks." Machine learning 20.3 (1995): 273-297.
[18] Shawe-Taylor, John, and Nello Cristianini. “Kernel methods for pattern analysis”. Cambridge university press, 2004.
[19] Scholkopf, Bernhard, and Alexander J. Smola. “Learning with kernels: support vector machines, regularization, optimization, and beyond.” MIT press, 2001.
[20] Wenping Wang, Zile Wei, Shengqi Yang and Yu Cao, "An efficient method to identify critical gates under circuit aging," 2007 IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2007, pp. 735-740.
[21] Chang, Chih-Chung, and Chih-Jen Lin. "LIBSVM: a library for support vector machines." ACM transactions on intelligent systems and technology (TIST) 2.3 (2011): 27.