近年來，隨著科技發展以及對於神經相關疾病的日趨重視生理訊號以及腦波訊號的監測系統的需求也越來越高，從行動裝置上獲得監測資訊或是直接製成一個閉迴路的系統來抑制及治療各種神經疾病(如：癲癇、帕金森氏症等等)，將整個系統整合成一個系統晶片也越發受到重視。
本論文為了配合植入式的整合型偵測腦波(EEG)閉迴路控制晶片，提出了一個新的建立在Level-crossing(LC)及SAR(Successive-approximation)基礎下的新的LC-SAR ADC架構。該架構基於CMOS 180nm製程並工作於單一一個0.9V電源供應下的同時可以接收當共模電壓(VCM)為0.9時3.06Vpp輸入訊號範圍。此架構使用差動輸入來消除偶次項諧波失真並同時結合SAR作為其量化器來提高SNDR和降低原本所需的超取樣率(Oversampling Ratio, OSR)及SAR架構原本所需的電容大小；運用delta sampling的方式並配合LC的概念使用在比較器前端加入判斷切換輸入端的方法來省下原本LC ADC需要至少兩個比較器的缺點，同時，在此架構的比較器中加入金氧半電容（金屬氧化物半導體電容 或Metal-Oxide-Semiconductor Capacitor 或MOSC）的陣列來同時控制及調整LC的域值電壓(Threshold Voltage)和比較器本身的偏移電壓(Offset Voltage)取代原本需要額外輸入來控制的閾值電壓。
在訊號頻寬4KHz及超取樣率OSR為16的情況之下，根據不同頻率的輸入訊號可自適應調整輸出取樣頻率、功耗及SNDR。在輸入訊號從接近4Hz到4KHz頻寬之間，輸出取樣頻率為1.98KHz~124KHz；經過測量功耗為580nW~763nW；SNDR為49.38dB~60.23dB，相當於有效位元數(ENOB)7.9~9.7位元；效能指標(FOM)大約落在109~303 fJ/conv，整個晶片(含PAD)面積為0.77mm2、核心電路面積則為0.1476mm2。

In recent years, with the development of technology and the increasing emphasis on neurological diseases, the demand for monitoring systems for physiological signals and brainwave signals has been increasing, and it has become more and more important to integrate the whole system into a system chip to obtain monitoring information from mobile devices or to make a closed-loop system to suppress and treat various neurological diseases (e.g., epilepsy, Parkinson's disease, etc.).
In this paper, a new LC-SAR ADC architecture based on Level-crossing (LC) and SAR is proposed for the implantable integrated EEG closed-loop control chip. The architecture is based on CMOS 180nm process and operates on a single 0.9V supply while receiving a 3.06Vpp input signal range when the common mode voltage (VCM) is 0.9.
This architecture uses differential input to eliminate even-order harmonic distortion and combines SAR as its quantizer to improve SNDR and reduce the required oversampling ratio (OSR) and capacitor size of the original SAR structure. Delta sampling is used in combination with the LC concept, and a method of judging and switching the input end is added to the front end of the comparator to eliminate the disadvantage of at least two comparators required in the original LC ADC. Additionally, a MOS capacitor (Metal-Oxide-Semiconductor Capacitor or MOSC) array is added to the comparator in this architecture to simultaneously control and adjust the threshold voltage of LC and the offset voltage of the comparator, replacing the need for additional input to control the threshold voltage.
With a signal bandwidth of 4KHz and an oversampling rate of 16, the output sampling frequency, power consumption, and SNDR can automatically be adapted to different frequencies of the input signal. The power consumption is 264nW~420nW, SNDR is 49.38dB~60.23dB, which is equivalent to the effective number of bits (ENOB) of 7.9~9.7bits, performance index (FOM) is about 109~303 fJ/conv, the area of the whole chip (including PAD) is 0.77mm2, and the core area is 0.1476mm2.

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