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研究生: 池任傑
Chih, Jen-Chieh
論文名稱: 應用於快速鎖定鎖相迴路之片斷線性相位頻率偵測器
Piecewise-Linear Phase Frequency Detector for Fast-Lock Phase-Locked Loops
指導教授: 許雅三
Hsu, Yar-Sun
邱瀞德
Chiu, Ching-Te
口試委員: 劉建男
許雅三
邱瀞德
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2011
畢業學年度: 99
語文別: 英文
論文頁數: 46
中文關鍵詞: 相位頻率偵測器鎖相迴路快速鎖定迴路頻寬
外文關鍵詞: phase-frequency detector (PFD), phase-locked loop (PLL), fast acquisition, loop bandwidth
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  • 這篇論文提出了一個新的非線性相位頻率偵測器架構,能夠同時達到快速鎖定與良好的輸出訊號抖動。片段線性相位頻率偵測器讓鎖定時間與輸出訊號抖動不再相互影響,因此相對於現有的一些架構在設計上擁有更多的彈性。當輸入訊號與回授訊號的相位差超過180度,片段線性相位頻率偵測器的調整機制會啟動,使與相位差成正比的電流量對迴路濾波器進行額外的充電或是放電以加快鎖定所需的時間。要是輸入訊號與回授訊號的相位差小於180度,則片段線性相位頻率偵測器的輸出波形與傳統的線性相位頻率偵測器相同來保持良好的輸出訊號抖動。為了要加快鎖定時間,非線性相位頻率偵測器的想法已經被討論了一段時間。即便如此,非線性相位頻率偵測器比起傳統的架構幾乎都複雜不少。而現存一些具備簡單架構的相位頻率偵測器卻都有它們各自的缺點。片段線性相位頻率偵測器是以傳統的架構做為基礎去做改良,所以對於晶片面積來說並沒有明顯的增加,它的架構很簡單但是卻能有效地解決先前架構所擁有的問題。除此之外,在這篇論文所提出的架構裡,兩個電荷幫浦每單位相位的充、放電量都經過數學算式的推導與分析來選擇最適合的值。因此不管是穩定性或是電路所消耗的功率都能夠達到最佳化。相較於傳統線性相位頻率偵測器,模擬結果顯示片段線性相位頻率偵測器的鎖定時間能夠有68%的提升,同時能夠維持良好的輸出訊號抖動。在這篇論文中,鎖相迴路的最高輸出頻率操作在2.5GHz。


    In this paper, a new structure of the nonlinear PFD is proposed to achieve fast lock as well as small output jitter. The proposed Piecewise-Linear PFD has more flexibility than previous designs, since the lock time and the output jitter of the PLL are no longer tradeoffs. When the phase difference of the reference and the feedback signal is larger than π, additional charging or discharging current is injected to the loop filter to accelerate the lock process. On the other hand, to keep the jitter small, the Piecewise-Linear PFD acts just like the conventional linear PFD while approaching lock. The concept of the nonlinear PFD has been discussed for a period of time to accelerate the acquisition time. Nevertheless, the structure of the nonlinear PFD is often more complicated than the conventional one. On the contrary, the existing simpler structures have their own disadvantages. The Piecewise-Linear PFD does not increase the chip area since the overhead is limited. The structure is simple but it does solve some flaws of the previous nonlinear PFD designs. In addition, the current source and current sink of two charge pumps in the proposed scheme have been proven to be the reasonable values by mathematical analysis. Thus, not only the stability but also the power consumption can be optimized. The post-simulation results show that a speedup of 68% can be achieved with comparison to the conventional PLL. Moreover, the jitter is almost the same. The output frequency of the PLL is up to 2.5GHz.

    List of Figures..........6 List of Tables..........8 1 Introduction..........9 2 Fundamentals of Phase-Locked Loops..........13 2.1 Phase Frequency Detector..........13 2.2 Charge Pump..........16 2.3 Loop Filter..........18 2.4 Voltage-Controlled Oscillator..........19 2.5 Frequency Divider..........22 3 Proposed Piecewise-Linear Phase Frequency Detector..........23 4 Simulation Results, Measurement Results and Performance Summary..........38 5 Conclusion and Future Work..........43 References..........45

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