基於規則與模式實現嵌入式元件自動連接｜國立清華大學博碩士論文庫

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研究生：	戴維政 Dai, Wei-Zheng
論文名稱：	基於規則與模式實現嵌入式元件自動連接 Enabling Rule-and-Pattern-Based Auto-Completion of Inter-Component Connection
指導教授：	周百祥 Chou, Pai H.
口試委員:	韓永楷 Hon, Wing-Kai 謝孫源 Hsieh, Sun-Yuan
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2021
畢業學年度：	109
語文別：	英文
論文頁數：	38
中文關鍵詞：	自動連接、協作平台、物聯網裝置、嵌入式系統、電腦輔助設計
外文關鍵詞：	Autocompletion, Bus allocation, Interface selection, Schematic completion
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設計嵌入式系統的一項必要任務是決定元件間的針角應該如何以導線連接成為完整的電路，
但是因為相對低階，很容易出錯。現有的解法一種是自動合成這些接線，或者提供一個大致
上已設計好但仍可以參數化的平台，但兩者皆無法尊重使用者在接線或元件選擇的偏好。其
他工具則因演算法複雜度過高，或因為不容易定義元件模型，而導致實用性低。因此，許多
嵌入式系統只好以手動方式完成低階的電路，但是一旦出錯，經常需要重新洗板打件導致專
案延宕而付出嚴重的代價。
為了解決上述問題，我們提出一套新的設計輔助工具，能夠提示與自動完成元件間針角
對針角的連線。我們將元件的介面與連線建模，使用的是稱為旗標圖形(semagraph)的一種
新穎的資料結構，不止能以拓撲表達連線，更能利用頂點與邊相對應的係數表達現有、該
有、可有的連線狀態。我們使用子圖同構，自動找出可能的下一步連接組合作為提示。根據
使用者的選擇，經過後處理，再自動檢查連接後的電路是否有效或完整。這種做法優勢在於
提供高階的表達式，讓建模時能夠把複雜的介面清楚地定義成介面模型，同時有擴允性，模
組化，不會因為要能配合設計師的偏好而需要修改到核心演算法。本論文把概念套用在實際
嵌入式系統最常使用的幾種介面協定上，示範本工具在輔助設計的優勢。

Connecting wires between electronic components is a necessary design task that is error-prone due
to the relatively low-level nature. Existing solutions force designers to accept either synthesized
solutions without being given a chance to choose their preferred connection among valid alternatives
or ready-to-use platforms that may not use components of the designer’s choice. Other tools may
suffer from intractible complexity or difficulty to construct a library of such bus models. As a result,
designers of embedded systems often resort to manual interfacing between components, but they often
pay a heavy price in refabrication cost of hardware and significant delay in product delivery.
To address these problems, we propose a new methodology where the tool can suggest and autocomplete
connections that need to be made between the pins of the components. The component
interface is modeled using a novel data structure called a semagraph, which can capture the state
of connection, i.e., existing and expected wires, precisely and concisely in terms of coefficients on
the vertices and edges of the graph. A subgraph isomorphism subroutine detects possible solutions to
suggest for auto-completion, and the user’s choice is applied and post-processed before being checked
for completeness based on protocol-specific rules. This approach makes it much more manageable to
define complex interfacing models with expandability without having to modify the core algorithm
while accommodating the user’s preference. This thesis demonstrates the claimed advantages by
applying the methodology to several of the most commonly used interfacing protocols in real-world
embedded systems.

Introduction 1
1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Background and Related Work 4
1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Microcontroller Units (MCU) . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 UART and GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Serial Busses (SPI, I2C, I2S, ...) . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Advanced Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Automatic Schematic Completion . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Platform-based Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Constraint-based Interface Synthesis . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Circuit Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Methodology 11
1 Overview of System Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Interface Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Bus Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 Schematic Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Technical Approach 16
1 Overview of Interface Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.1 Bus Roles and Wiring Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.2 Allocation of Roles and Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.3 Semaphore Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1 Semagraph Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2 Semagraph Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3 Semagraph Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Interface Modeling and Realization . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Bus Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3 Schematic Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Evaluation 33
1 Tool Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2 Expressiveness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Conclusions and Future Work 36
1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Appendix 39
                                

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