As technology advances, 3D-ICs are introduced for alleviating the interconnect scaling problem coming with shrinking feature size and increasing integration density. In 3D-ICs, one of the key challenges is the vertical Through-Silicon-Vias (TSVs) used for different device layers connection. In this thesis, we present a 3D-ICs fixed-outline floorplanner with TSV assignment and pin assignment. To find a good slicing floorplan, we generalize the notion of slicing tree based on the principle of Deferred Decision Making (DDM). Because of DDM, one slicing tree actually corresponds to a huge number of slicing floorplan solutions. We also consider the exact position of TSVs, which is never addressed in the previous works. Several techniques are also proposed to further optimize the total wirelength, such as whitespace re-distribution, non-boundary pin assignment. Experimental results show that our approach is efficient and effective for wirelength optimization and fast runtime.

由於製程越做越小導致晶片上之連線問題複雜化，三維立體積體電路視為一種可以消除連線問題複雜化的方法。然而，直通矽晶穿孔用來連接不同層的技術在三維立體積體電路設計下是設計的問題之一。這篇論文主要探討在三維立體積體電路設計下之平面規劃、分派直通矽晶穿孔及分派腳位之方法。首先，為了找到一個好的平面規劃，我們利用一種延後決定最後平面規劃結果的方法來產生一個不錯的解。接著透過重新規劃可用空間的方法讓直通矽晶穿孔能放在不錯的位置上。另外值得一提的是直通矽晶穿孔的位置是絕對位置；也就是說，我們準確地找到直通矽晶穿孔在該平面規劃下的座標。最後，考慮腳位在三維立體積體電路下的位置。不同於傳統的考量，我們將考慮腳位可以放置在每一個區塊範圍內的任意位置上。透過實驗結果得知，我們除了有效找到直通矽晶穿孔的絕對位置之外，不同於傳統的分派腳位位置，我們能夠獲得更好的總線長；同時，我們的方法也透過有效的整合，讓執行時間能在短時間內完成。

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