應用堆疊式高介電穿隧氧化層與高功函數金屬閘極於電荷捕捉式快閃記憶體之電特性研究

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研究生：	何廷峻 Ting-Jyun He
論文名稱：	應用堆疊式高介電穿隧氧化層與高功函數金屬閘極於電荷捕捉式快閃記憶體之電特性研究 Investigation of applying stack High-K tunneling oxide and high work function metal gate to charge-trapping Flash Memory
指導教授：	張廖貴術 Kuei-Shu Chang-Liao
口試委員:
學位類別：	碩士 Master
系所名稱：	原子科學院 - 工程與系統科學系 Department of Engineering and System Science
論文出版年：	2008
畢業學年度：	96
語文別：	中文
論文頁數：	122
中文關鍵詞：	快閃記憶體、穿隧氧化層、高介電材料、高功函數電極、SONOS 、PIII
相關次數：	點閱：4 下載：0
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當浮動閘極結構之快閃記憶體無法滿足元件微縮的發展時，而SONOS 結構快閃記憶體再度成為研究的方向，然而以氮化矽當作電荷捕捉層之SONOS 快閃記憶體於次微米時代之後，無法再藉由降低穿隧氧化層的方式提高寫入操作速度，況且元件的電荷保存力也將有所疑慮。因此希望以高介電材料的應用達到較佳的工作特性與可靠度特性。
本論文的研究重點主要包含三個方向：
(一) 採用能帶工程理論，設計堆疊式之穿隧氧化層，搭配高介電材
料，應用於電荷捕抓式快閃記體元件，並觀察比較其綜合之電特性表現。(本章實驗樣品為電晶體結構)
(二) 選用較高功函數金屬閘極MoN 應用於電荷捕捉式快閃記憶中，觀察比較此金屬閘極的變動將對元件電特性有何改善與影
響。(本章實驗樣本包含電容結構與電晶體結構)
(三) 利用電漿沈浸離子佈植氮化電荷捕抓式快閃記憶體，觀察用此法氮化對元件電特性有何改善與影響。(本章實驗樣本為電容結構)
實驗結果可以觀察到堆疊式高介電穿隧氧化之設計，有助於增進寫入速度，並且依然保有不錯的電荷保存力。而選擇較高功函數之金屬閘極，將有助於抹除特性的有效改善。

目錄

誌謝.......................................................I
摘要......................................................Ⅳ
目錄......................................................Ⅴ
圖目錄....................................................Ⅷ
表目錄....................................................XI

第一章 序論................................................1
1 前言..................................................1
2 快閃記憶體面臨問題....................................2
3 SONOS 快閃記憶體的結構與優點..........................2
4 SONOS 快閃記憶體面臨的問題............................4
5 研究目的..............................................5
6 各章摘要..............................................6

第二章 快閃記憶體元件操作方法.............................13
1 寫入與抹除方法.......................................13
1.1 通道熱電子注入寫入................................13
1.2 F-N 穿隧寫入......................................14
1.3 F-N 穿隧抹除......................................15
2 電荷保持力...........................................16
3 耐力.................................................17
4 干擾.................................................18

第三章 實驗規劃與元件製程.................................30
1 實驗規劃.............................................30
2 電容元件製程.........................................31
2.1 晶片刻號及零層曝光................................31
2.2 晶背歐姆接觸......................................31
2.3 沈積穿隧氧化層、電荷捕抓層與阻擋氧化層............32
2.4 堆疊金屬閘極(Metal Gate)與上電極..................32
2.5 定義電容圖形與完成電容結構........................33
3 電晶體元件製程.......................................33
3.1 晶片刻號及零層曝光................................33
3.2 主動區定義........................................34
3.3 LOCOS 沈積........................................35
3.4 成長閘極穿隧氧化層................................36
3.5 沈積電荷捕抓層、阻擋氧化層、金屬閘極..............36
3.6 閘極定義與離子佈植................................37
3.7 堆疊隔絕保護層....................................38
3.8 接觸窗與金屬連線..................................38

第四章 堆疊式高介電材料穿隧氧化層對快閃記憶體元件電特性
       影響...............................................46
1 研究背景與目的.......................................46
2 實驗規劃與製程.......................................48
3 結果與討論...........................................50
3.1 快閃記憶體以通道 F-N 穿隧寫入/抹除操作特性分析比較50
3.2 快閃記憶體可靠度分析比較..........................53
3.3 快閃記憶體通道熱電子寫入與帶對帶抹除操作特性分析比
        較................................................56
4 結論.................................................58

第五章 不同功函數金屬閘極對快閃記憶體元件電特性影響.......79
1 研究背景與目的.......................................79
2 實驗規劃與製程.......................................81
2.1 不同功函數金屬電極應用於快閃記憶體電容結構........81
2.2 不同功函數金屬電極應用於快閃記憶體之電晶體結構....82
3 結果與討論...........................................83
3.1 不同功函數金屬電極應用於快閃記憶體電容結構電性分析83
3.2 不同功函數金屬電極應用於快閃記憶體電晶體結構電性分
        析................................................84
3.2.1 通道FN (Channel F-N)穿隧寫入/抹除操作特性分析..85
3.2.2 快閃記憶體可靠度分析比較.......................86
3.2.3 通道熱電子(CHEI)寫入與帶對帶抹除操作特性分析比
           較.............................................87
4 結論.................................................89

第六章 電漿沈浸離子佈值氮化電荷捕捉式快閃記憶體介電層之
       研究..............................................111
1 研究背景與目的......................................112
1.1 電漿沈浸離子佈植技術原理與優點...................112
1.2 高介電材料於電荷捕抓式快閃記憶體中的發展.........112
1.3 高介電材料所面臨的問題...........................113
1.4 於電荷捕抓式快閃記憶體介電層佈植氮離子...........113
2 實驗規劃與製程......................................114

第七章 結論與建議....................................... 117
1 結論................................................117
2 建議................................................118

參考文獻.................................................120

                                

參考文獻

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