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研究生： 書里拉
Surya Chandra Gulipalli
論文名稱： 適用於微電網嚴峻併網情境下之進階三相鎖相迴路與鎖頻迴路技術
Advanced Three-Phase Phase-Locked Loop and Frequency-Locked Loop Techniques for Micro-Grid Synchronization Under Adverse Conditions
指導教授： 朱家齊
Chu, Chia-Chi
口試委員: 吳有基
Wu, Yu-Chi
連國龍
Lian, Kuo-Lung
張文恭
Chang, Wen-Kung
謝秉璇
Hsieh, Ping-Hsuan
張淵智
Chang, Yuan- Chih
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2023
畢業學年度： 111
語文別： 英文
論文頁數： 102
中文關鍵詞： 鎖相迴路 (PLL) 、鎖頻迴路 (FLL) 、電網頻率 、相位角 、電網同步 、電力系統諧波
外文關鍵詞： Phase-locked loop (PLL), Frequency-locked loop (FLL), grid frequency, phase-angle, grid synchronization, power system harmonics
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    Reliable, smooth and safe operation of a Micro Grid requires magnitude, phase angle and frequency information of the fundamental positive sequence voltage component of the grid for its synchronization, operation and control purposes. Over the years, different synchronization devices with versatile approaches to estimate these grid parameters were reported in the literature. They can be broadly categorized into two groups: open-loop methods and closed-loop ones. Closed-Loop Synchronization (CLS) techniques, modelled by having at least a single feedback signal in their designs, had gained more research attention than open-loop ones. Phase-Locked Loops (PLLs) and Frequency-Locked Loops (FLLs) are two broad categories of CLS techniques. Generally speaking, PLLs are implemented either in the synchronous (dq) reference frame (SRF-PLL) or abc frame(EPLL), while FLLs are realized in the stationary (alphabeta) reference frame. All these are equivalent to each other to a certain degree at the low-frequency range. However, unlike other two kinds, FLLs primarily focus on locking the frequency information rather than the phase information. These models are susceptible to a poor performance, especially during grid imbalances and DC offsets. The focus of this research work is to enhance the performance of FLLs and PLLs by new design models and filters. A new cascaded Multiple Delayed Signal Cancellation (CMDSC) filter is proposed to address the adverse grid conditions that include DC bias and unsymmetrical harmonics. The proposed filter advantages over the existing delay-based filters is analysed. It's recursive form implementation in alphabeta frame and dq frame is presented.
    The accomplishments of this research work on PLLs can be encapsulated as follows:
    1) Dynamical Performance Enhancement of Synchronous Reference Frame Phase-Locked Loop by K-Factor Method based controller design.
    2) Proposal of a Novel Dual Synchronous Reference Frame Phase Locked Loop(DSRF-PLL) that can instantly track the phase angle variations of the grid.
    3) CMDSC filters based pre-filtered DSRF-PLL model is investigated and performance is compared with the pre-filtered SRF-PLLs under adverse grid conditions.
    4) Performance of existing In-loop filtered SRF-PLLs from literature is enhanced with the In-loop filtered DSRF-PLL counterparts.
    The accomplishments of this research work on FLLs can be encapsulated as follows:
    1) Integration of MDSC filters at the In-loop filtering stage of FLLs and comparison with earlier models presented in literature using CDSC and CBF filters, employing Proportional Integral (PI) controller and tuning at low band widths by symmetrical optimum method.
    2) A K-factor method based controller design for FLLs is investigated. This method can embed the desired phase boosts at desired cross over frequencies. The additional pole introduced by this method is equivalent to a complex bandpass filter (CBF) in-loop filtered FLL which gives an additional advantage to eliminate high frequency disturbances.
    3) A very high speed FLL is designed using K-factor method. Such a high speed designs are susceptible to lower order harmonics. So as to improve the performance under symmetrical disturbances, previously presented three filters are studied at pre-filtering stage and performance is analyzed.

    Abstract (Chinese) I Abstract III Acknowledgements (Chinese) V Acknowledgements VI Contents VII List of Figures X List of Tables XIII Nomenclature XVII 1 Introduction 1 1.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Cascaded Multiple Delayed Signal Cancellation filter . . . . . . . . 4 1.3 Dynamical Performance Enhancement of SRF-PLL using K-factor Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 Novel Dual Synchronous reference frame phase Locked Loop . . . . 6 1.5 In-loop Filtered and Pre-Filtered DSRF-PLL . . . . . . . . . . . . . 6 1.6 Performance Enhanced Frequency Locked Loop . . . . . . . . . . . 7 2 Cascaded Multiple Delayed Signal Cancellation Filter 9 2.1 Complex Coefficient Filter . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Moving Average Filter . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Cascaded Delayed Signal Cancellation Filter . . . . . . . . . . . . . 13 2.4 Multiple Delayed Signal Cancellation(MDSC) Filter . . . . . . . . . 14 2.5 Cascaded Multiple Delayed Signal Cancellation(CMDSC) Filter . . 19 2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 Dynamical Performance Enhancement of SRF-PLL Using K-Factor Method 23 3.1 SRF-PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1.1 Small Signal Model of SRF-PLL . . . . . . . . . . . . . . . . 26 3.2 Symmetrical Optimum method . . . . . . . . . . . . . . . . . . . . 27 3.3 K-Factor Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.1 Quality Factor Analysis . . . . . . . . . . . . . . . . . . . . 31 3.3.2 Phase Error Compensation . . . . . . . . . . . . . . . . . . . 33 3.4 Simulation Verifications . . . . . . . . . . . . . . . . . . . . . . . . 35 3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4 Novel Dual Synchronous reference frame phase Locked Loop 39 4.1 DSRF-PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.1.1 Small Signal Model of DSRF-PLL . . . . . . . . . . . . . . . 42 4.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5 In-Loop Filtered and Pre-Filtered DSRF-PLL 47 5.1 In-Loop Filtered DSRF-PLL . . . . . . . . . . . . . . . . . . . . . . 47 5.1.1 Simulation Verifications . . . . . . . . . . . . . . . . . . . . 50 5.2 Pre-Filtered DSRF-PLL . . . . . . . . . . . . . . . . . . . . . . . . 54 5.2.1 Simulation Verifications . . . . . . . . . . . . . . . . . . . . 55 5.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6 Performance Enhanced Frequency Locked Loop 60 6.1 Standard FLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.2 In-loop Filtered low bandwidth FLL using PI controllers . . . . . . 64 6.2.1 Parameter Tuning . . . . . . . . . . . . . . . . . . . . . . . . 66 6.2.2 Experimental Verifications . . . . . . . . . . . . . . . . . . . 71 6.3 Pre-Filtered high bandwidth FLL using K-factor controllers . . . . 75 6.3.1 Phase and Magnitude Error Compensation Design . . . . . . 76 6.3.2 Experimental Verifications . . . . . . . . . . . . . . . . . . . 78 6.3.3 CMDSC Pre-Filtered FLL under Adverse Grid Conditions . 81 6.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7 Conclusion 88 Bibliography 92 Vita 102

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