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研究生： 蔡政宏
Jeng-Horng Tsai
論文名稱： 一個數位至類比轉換器的嵌入式內建自我測試方法
An Embedded Built-In-Self-Test Approach for Digital-to-Analog Converters
指導教授： 張慶元
Tsin-Yuan Chang
口試委員:
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2001
畢業學年度： 89
語文別： 英文
論文頁數： 51
中文關鍵詞： 差異非線性 、整體非線性 、參數測試 、內建自我測試 、數位至類比轉換器
外文關鍵詞： DNL, INL, Parametric Test, BIST, DAC
相關次數： 點閱：1  下載：0 
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    • 在系統晶片(SOC)的測試上，要如何測試類比元件是一件很困難的問題，尤其是這些元件都在晶片裡面。所以我們選用內建自我測試(BIST)的方法來增加可控制性(controllability)和觀察能力(observability)，以及減少自動測試儀器的負擔，進而減少測試的花費。
    我們提出了一個內建自我測試的方法來測試數位至類比轉換器(DACs)的一些參數。這些參數包括：偏移誤差(offset error)，增益誤差(gain error)，差異非線性(differential non-linearity)，和整體非線性(integral non-linearity)。測試這些基本的參數我們可以驗證數位至類比轉換器的基本功能。我們提出的方法不需要許多準確的參考電壓，而且考慮到製程飄移的影響以及匹配(matching)的問題。

    偏移誤差、增益誤差、和差異非線性的測試是利用誤差放大器(Error Amplifiers)和比較器來做電壓的萃取和比較。利用誤差放大器可以準確的取出差異電壓(difference voltage)，而且不帶有直流位準的成分。比較器是用來檢查取出的差異電壓是不是在容忍的範圍內。整體非線性的測試是先把差異非線性測完，然後利用數位至類比轉換器的輸出去追負斜坡(negative ramp)電壓，如果追到了就產生派波給控制器去產生下一個輸入碼，這個方法是把電壓轉換成時間，再用系統的時脈(clock)對時間取樣，然後利用公式計算，就可以求得整體非線性。

    我們用八位元(8-bit)的數位至類比轉換器在台積電(TSMC) 0.35 μm 2P4M的製程下模擬。在5V操作下的八位元數位至類比轉換器，偏移誤差、增益誤差、和差異非線性的測試準確度在LSB/11 以下，也就是說利用這個方法可以測十位元(10-bit)的數位至類比轉換器。整體非線性的測試解析度和測試時間有關，測試時間愈長準確度愈高。

    Without a large number of precision reference voltages and with the consideration of matching problems, a built-in-self-test approach is proposed to test the parameters of digital-to-analog converter (DAC), which includes offset error, gain error, differential nonlinearity (DNL) error, and integral nonlinearity (INL) error. The proposed structure is designed and simulated in an 8-bit DAC by using TSMC 0.35 μm 2P4M process. The accuracy of offset error test, gain error test, and DNL test are all beneath LSB/11 for 8-bit DAC at 5V supply voltage, and the accuracy of INL test depends on the testing time. The longer testing time, the more accurate is.

    Abstract 1}Introduction 1.1}Motivation 1.2}Why BIST is Chosen? 2}Basic Characteristics of DAC 2.1}Parameters 2.2}Other Performance Limitations 3}Previous Works 3.1}Arabi's Work (1996) 3.2}Wen's Work (1998) 3.3}Huang's Work (2000) 4}The Proposed BIST Structure for DAC Testing 4.1}Differential Non-Linearity Test 4.1.1}Error Amplifier 4.1.2}Comparator with Auto-Zero Circuit and Track-and-Hold Stage 4.1.3}Control Signals Generator for DNL Test Circuit 4.1.4}Switches 4.2}Offset Error Test, Gain Error Test, and Selftest 4.3}Integral Non-Linearity Test 4.3.1}Negative Ramp Generator 4.3.2}High Speed Comparator 4.4}Controller and Test Procedure 5}Experimental Results 5.1}Simulation Results of DNL Test Circuit 5.2}Simulation Results of INL Test Circuit 5.2.1}Simulation Results of Negative Ramp Generator 5.2.2}Simulation Results of High Speed Comparator 5.3}Experimental Results of Some Examples 5.4}Area-Overhead 6}Conclusions 6.1}Future Work 6.2}Acknowledgment Appendix A}Hspice Codes of Pre-Simulation A.1}DNL Test Circuit A.2}Negative Ramp Generator A.3}High Speed Comparator B}Verilog Codes of Controller B.1}top module B.2}control module B.3}dnlf\/lag module B.4}inltest module B.5}inlf\/lag module B.6}inlf\/laga module B.7}inlcal module B.8}inl2n module B.9}inlnext module B.10}inlcount module B.11}counter module Bibliography

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