動態隨機存取記憶體（DRAM）時間參數的測試長久以來一直被認為是個複雜且耗時的過程。本論文針對目前市面上常見的同步動態隨機存取記憶體（SDRAM）提出整個系統化分析時間參數和硬體架構的方法，並且整理該記憶體電路中所有的延遲錯誤形態，我們發現傳統的函數錯誤模型沒辦法測試出某些跟時間參數相關的錯誤型態，也就是為什麼目前工業界的測試流程是在測試完函數錯誤後再額外測試時間參數，對於這些複雜的時間參數測試，我們利用延遲錯誤模型並提出簡單的測試方法來解決。

本論文針對這些時間參數，整理從SPICE電路模型得到的模擬結果提出四個延遲錯誤模型，分別為「控制器延遲錯誤模型（Controller Delay Fault Model）」、「分支位元線延遲錯誤模型（Sub-Bitline Delay Fault Model）」、「主位元線延遲錯誤模型（Main-Bitline Delay Fault Model）」及「讀取驅動器延遲錯誤模型（Read Driver Delay Fault Model）」，並且討論這些錯誤的激發條件和觀察條件，最後提出一個March的測試演算法，藉由測試這四個簡單且高階的延遲錯誤模型來確保記憶體時間參數的正確性，可以簡化原本複雜的測試流程，也可以縮短整體測試與錯誤診斷的時間。

最後，本論文也提出一個具有測試時間參數能力的內建式自我測試電路（Built-In Self-Test Circuit），相較於傳統的內建式自我測試電路有15.9%的額外硬體面積，而針對256-Mbit的同步動態隨機存取記憶體所提出的內建式自我測試電路佔該記憶體的硬體面積小於1%。

DRAM timing parameter testing has always been considered a complex and time-consuming process.
This thesis presents a systematic approach to analysis of the synchronous DRAM (SDRAM)
circuit and classification of all SDRAM delay failure modes. We show that certain failure modes
that are directly linked to existing timing parameters are not covered by traditional functional fault
models. Therefore, the current practice in the industry is to test the critical timing parameters separately,
in addition to testing the functional faults. In this thesis four delay fault models are proposed
to cover these critical timing parameters. The activation and observation conditions for these delay
faults are discussed and thus theMarch test solution is presented. The test can further be supported
by our proposed programmable BIST, which the area overhead is considered 15.9% compared to
conventional BIST, less than 1% compared to the memory die size. By only testing these four types
of delay faults, we can verify the correctness of timing specifications without traditional complex
patterns.

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