H.264/AVC 是由國際標準組織 (ISO)和國際電信聯盟 (ITU)所共同制定的，為目前最新的視訊編碼標準。相較於先前的視訊編碼標準，H.264/AVC提供近二倍的壓縮效率，但是複雜的運算也造成 H.264/AVC很難做到即時處理。其中可變長度解碼 (CAVLD)是解碼器最先處理的部分，因可變長度解碼的循序處理特性，其效能將會影響整個解碼器的效能。此外，在幀內/幀間預測 (intra/inter prediction)時，大量參考像素的讀取及運算是相當耗電的，不利於手持裝置使用 H.264/AVC視訊編碼標準。本論文所提出的可變長度解碼器利用領導零的個數 (NumLZ)和剩餘位元 (TBits)這二個特性來加速查表的過程，並且透過合併係數標誌 (CoeffToken)和號 (SIGN)這二個階段達到每個時脈周期 (clock cycle)可以解碼出一個以上的語法元素 (syntax element)，再加上時脈閘控 (clock gating)可以減少功耗36%。另外，在幀內/幀間預測器的部分，則使用暫存器來暫存已讀取參考像素和預測結果，對於幀內預測可減少參考像素讀取82%和功耗7%；對於幀間預測可減少參考像素讀取66%和功耗12%。
關

H.264/AVC is the latest video coding standard jointly developed by ITU-T VCEG and ISO/IEC MEPG. H.264/AVC enhances almost two times coding efficiency than prior video coding standards, but the high computational complexity makes it difficult to decode video in real-time even using high-end central process unit. Sequential CAVLD process is the bottleneck of performance, and mass reference pixel access and high computational complex of intra/inter prediction consume a lot of power. The proposed CAVLD uses the prosperities of codeword, numLZ and TBits, to speed up the table lookup process and decodes more than one syntax element by combining CoeffToken and SIGN stage. Besides, the CAVLD reduces at most 36% power consumption after applying the clock gating to shut down some functional blocks when they are unnecessary. Temp registers are used in the proposed intra/inter predictor to keep the accessed reference pixels and prediction result, and 82% reference pixel access is reduced and at most 7% power dissipation is saved in intra prediction and 66% reference pixels access is reduced and at most 12% power dissipation is saved in inter prediction.

[1]
A. Agarwal, S. Mukhopadhyay, A. Raychowdhury, K. Roy, and C. H. Kim, “Leakage Power Analysis and Reduction for Nanoscale Circuit”, IEEE Mirco, Vol. 26, pp.68-80, March-April 2006
[2]
M. Alle, J. Biswas, and S. K. Nandy, “High Performance VLSI Architecture Design for H.264 CAVLC Decoder”, International Conference on Application-specific Systems, Architectures and Processors (ASAP 2006), pp. 317-322, Sept. 2006
[3]
S. B. Choi and M. H. Lee , “High Speed Pattern Matching For a Fast Huffman Decoder”, IEEE Transactions on Consumer Electronics, Vol. 41, pp.97-103, Feb. 1995
[4]
H. C. Chang, C. C. Lin, and J. I. Guo, “Novel Low-Cost High-Performance VLSI Architecture For MPEG-4 AVC/H.264 CAVLC Decoding”, IEEE International Symposium on Circuits and Systems (ISCAS 2005), Vol. 6, pp. 6100-6113, 23-26 May 2005
[5]
B. S. Choi and J. Y. Lee, “Implementation of Area Efficient H.264/AVC CAVLC Decoder”, IEEE International Conference on IC Design and Technology (ICICDT 2009), pp.135 – 138, 18-20 May 2009
[6]
T. W. Chen, Y. W. Huang, T. C. Chen, Y. H. Chen, C. Y. Tsai, and L. G. Chen, “Architecture Design of H.264/AVC Decoder with Hybrid Task Pipeline for High Definition Videos”, IEEE International Symposium on Circuits and Systems (ISCAS 2005), Vol. 3, pp.2931-2934, 23-26 May 2005
[7]
H.264/AVC JM Reference Software, Available: http://iphome.hhi.de/suehring/tml/download/
[8]
Joint Video Team of ITU-T and ISO/IEC JTC 1, “Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification, ITU-T Rec. H.264 | ISO/IEC 14496-10 AVC,” Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVT-G050, March 2003.
[9]
J. Kao, S. Narendra, and A. Chandrakasan, “Subthreshold Leakage Modeling and Reduction Techniques”, IEEE/ACM International Conference on Computer Aided Design (ICCAD 2002), pp.141-148, 10-14 Nov. 2002
[10]
T. A. Lin, S. Z. Wang, T. M. Liu and C. Y. Lee, “An H.264/AVC Decoder With 4x4 Block Level Pipeline”, IEEE International Symposium on Circuits and Systems (ISCAS 2005), Vol. 2, pp. 23-26, May 2005
[11]
H. Y. Lin, Y. H. Lu, B. D. Liu, and J. F. Yang, “A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder”, IEEE Transactions on Multimedia, Vol. 10, pp. 31-42, Jan. 2008
[12]
T. A. Lin, T. M. Liu and C. Y. Lee, “A Low-Power H.264/AVC Decoder”, IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT 2005), pp. 283-286, April 2005
[13]
G. G. Lee, C. C. Lo, Y. C. Chen, S. F. Lei, H. Y. Lin, and M. J. Wang, Low Complexity and High Throughput VLSI Architecture for AVC/H.264 CAVLC Decoding”, IEEE International Symposium on Circuits and Systems (ISCAS 2009), pp.129-1232, 24-27 May 2009
[14]
A. Mukherjee, N. Ranganathan, and M. Bassiouni, “Efficient VLSI Design for Data Transformation of Tree-Based Codes”, IEEE Transactions on Circuits and Systems, Vol. 38, pp.306-314, March 1991
[15]
A. Mukherjee, N. Ranganathan, J. W. Flieder, and T. Acharya, “MARVLE: A VLSI Chip for Data Compression Using Tree-Based Codes”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.1, pp.203-214, June 1993
[16]
M. Oh, W. Lee, and J. Kim, “Design of High Speed CAVLC Decoder for H.264/AVC”, IEEE Workshop on Signal Processing Systems, pp.325-330, 17-19 Oct. 2007
[17]
H. Park and V. K. Prasanna, “Area Efficient VLSI Architectures for Huffman Coding”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 40, pp.568-575, Sept. 1993
[18]
M. Parlak, Y. Adibelli, and I. Hamzaoglu, “A Novel Computational Complexity and Power Reduction Technique for H.264 Intra Prediction”, IEEE Transactions on Consumer Electronics, Vol.54, pp. 2006-2014, November 2008
[19]
I. E. G. Richardson, “H.264 and MPEG-4 Video Compression”, John Wiley, 2003,
[20]
B. J. Shieh, Y. S. Lee, and C. Y. Lee, “A New Approach of Group-Based VLC Coded System with Full Table Programmability”, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 11, pp.210-221, Feb 2001
[21]
J. R. Smith, “The H.264 Video Coding Standard”, IEEE Multimedia, Vol.13, pp.86-90, Oct.-Dec. 2006
[22]
T. Wiegand, G. J. Sullivan, G. Bjøntegaard, and A. Luthra, “Overview of the H.264/AVC Video Coding Standard”, IEEE Transactions on Circuits and Systems for Video Technology, Vol.13, pp.560-576, July 2003
[23]
T. Wiegand, H. Schwarz, A. Joch, F. Kossentini, and G. J. Sullivan, “Rate-Constrained Coder Control and Comparison of Video Coding Standards”, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 13, pp.688-703, July 2003
[24]
B. W. Y. Wei and T. H. Meng, “A Parallel Decoder of Programmable Huffman Codes”, IEEE Transactions on Circuits and Systems for Video Technology, Vol.5, pp.175-178, April 1995
[25]
Y. N. Wen, G. L. Wu, S. J. Chen, and Y. H. Hu, “Multiple-Symbol Parallel CAVLC Decoder for H.264/AVC”, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2006), pp. 1240-1243, 4-7 Dec. 2006
[26]
D. Wu, W. Gao, M.Z. Hu, and Z.Z. Ji, “A VLSI Architecture Design of CAVLC
[27]
YUV Test Sequence, Available: http://trace.eas.asu.edu/yuv/index.html
[28]
G. S. Yu, and T. S. Chang, “A Zero-Skipping Multi-Symbol CAVLC Decoder for MPEG-4 AVC/H.264”, IEEE International Symposium on Circuits and Systems (ISCAS 2006)
[29]
YUV Test Sequence, Available: http://ftp3.itu.ch/av-arch/jvt_site/draft_conformance