一個應用於HEVC中的進行反量化及反離散餘弦變換之高效率管線化超大型積體電路架構

簡易檢索 / 詳目顯示

回結果列表

研究生：	陳乃鈞 Chen, Nai Chun
論文名稱：	一個應用於HEVC中的進行反量化及反離散餘弦變換之高效率管線化超大型積體電路架構 An Efficient Pipelined VLSI Architecture for Inverse Quantization and Discrete Cosine Transform in H.265/HEVC
指導教授：	林永隆 Lin, Youn Long
口試委員:	王家祥 Wang, Jia Shung 郭皇志 Kuo, Huang Chih
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2015
畢業學年度：	103
語文別：	英文
論文頁數：	44
中文關鍵詞：	HEVC 、硬體、管線化
外文關鍵詞：	HEVC, Hardware, Pipelined
相關次數：	點閱：3 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

在本論文中，我們提出一個應用於HEVC main profile的包含系數掃描、反量化以及反離散餘弦變換之硬體架構。本設計支援4x4，8x8以及16x16大小的轉換方塊。架構中包含了一個掃描單元、一個用於反量化的雙階層管線化單元、一個可重複利用的反離散餘弦變換單元，以及相對應的控制單元。本設計可支援3840x2160解析度的60FPS影片。

We propose a hardware implementation including coefficient scanning, inverse quantization and inverse discrete cosine transform for HEVC main profile in this thesis. The design supports 4x4, 8x8 and 16x16 sized transform blocks. It includes a scanning unit, a two-stage pipelined architecture for inverse quantization, a reusable architecture for inverse discrete cosine transform and corresponding control units. The proposed design can support real time decoding of 3840 x 2160 video at 60 fps.

Abstract    i
Contents    ii
List of Figures    iii
List of Tables    iv
Chapter 1 Introduction    1
Chapter 2 IQ And IDCT Algorithm    3
2.1 Coefficient Scanning/IQ/IDCT Overview    3
2.2 Partitioning    4
2.3 Coefficient Flags    5
2.4 Decoding Process    6
2.5 Coefficient Scanning    9
2.6 Inverse Quantization    11
2.7 Inverse Discrete Cosine Transform    13
Chapter 3 Related Work    15
Chapter 4 Proposed Architecture    17
4.1 Overview of the Proposed Architecture    17
4.2 Global Memory Organization    19
4.3 Coefficient Scanning Datapath    21
4.4 Inverse Quantization Datapath    23
4.5 Inverse Discrete Cosine Transform Datapath    25
4.6 Cycle Analysis    27
Chapter 5 Experiment Result    28
5.1 Implementation and Verification    28
5.2 Synthesis Result    30
5.3 Simulation Result    31
5.4 Comparison    32
Chapter 6 Conclusions    33
REFRENCES    34


                                

[1] ITU-T and ISO/IEC JTC 1, "Advanced Video Coding for Generic Audio-Visual Services," ITU T Rec.H264, Feb. 2014.
[2] B. Bross, W.-J. Han, J.-R. Ohm, G. J. Sullivan, and Y.-K. Wang, T. Wiegand , " High Efficiency Video Coding (HEVC) text specification draft 10 (for FDIS & Consent)," in JCTVC-L1003, Switzerland, Jan. 2013.
[3] S.-T. Hsu, "An Efficient VLSI Architecture for Inverse Quantization and Inverse Discrete Cosine Transform in H.264/AVC FRExt," July 2007.
[4] P.Kumar, Sang-Yoon Park, B.Kumar, Khoon-seong Lim, and Chuohao Yeo, "Efficient Integer DCT Architectures for HEVC," IEEE Transactions on Circuits and Systems for Video Technology, volume24, issue 1, pp. 168-178, 2014.
[5] Ruhan Conceição, José Cláudio de Souza Jr., Ricardo Jeske, Bruno Zatt, Marcelo Porto, and Luciano Agostini, "Low-Cost and High-Throughput Hardware Design for the HEVC 16x16 2-D DCT Transform," Journal of Integrated Circuits and Systems v.9 , pp. 25-35, 2014.
[6] T. Dias, N. Roma, and L. Sousa, "High Performance Multi-Standard Architecture for DCT Computation in H. 264/AVC High Profile and HEVC Codecs," Conference on Design & Architectures for Signal and Image Processing, pp. 14-21, 2013.
[7] E. Kalali, E. Ozcan, and O. M. Yalcinkaya, I Hamzaoglu, "A Low Energy HEVC Inverse DCT Hardware," in IEEE Int. Conference on Consumer Electronics, Berlin, Sep. 2013.
[8] Introduction to the Quartus II software, San Jose: Altera Corporation, 2010.
[9] ModelSim-Altera Software Simulation User Guide, San joes: Altera Corporation, 2013.
[10] F. Bossen, HM Software Manual, (JCT-VC), 2013.
[11] W.-H. Chen, C. H. Smith, and S. C. Fralick "A fast computational algorithm for the discrete cosine transform," IEEE Transactions on Communications, vol.25, No.9, pp.1004-1009 Sep. 1977.
[12] Mathias Wien, High Efficiency Video Coding: Coding Tools and Specification
. Springer Berlin Heidelberg, 2014, ch.1, pp. 6.

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文