近年來，隨著積體電路之功能與複雜度提升，半導體製程技術的進步，晶片面積不斷增大，不但增加IC成本，也同時影響良率，使得電晶體的尺寸縮小，速度提高；但當電晶體通道長度縮到數十奈米；電晶體的開關特性不易控制。因此，縮減二維平面上電晶體的尺寸大小之外，人們也開始研究垂直方向的堆疊，亦即是三維積體電路的概念。TSV（Through Silicon Via）是目前三維積體電路的主要連接技術，由於TSV是由長直且大面積的銅所製成，當訊號通入TSV後會在基板上引發耦合雜訊。此種TSV引發的雜訊，與二維電路中之耦合情況不同，因此，在本篇論文中，我們將研究TSV所產生之雜訊對電路端點的影響。
本論文先詳述TSV電路中雜訊的由來，比較在不同結構參數下，雜訊的大小，以其對附近電路之影響範圍。首先，我們利用2D元件軟體的模擬，分析TSV訊號對於矽基板電位的影響及分佈。接著，藉由分析不同頻率的訊號入穿矽孔道後，會對周遭電路的影響程度，本論文提出一些三維積體電路相關中TSV之設計準則。同時，本論文針對不同的保護環的設計，評估雜訊抑制能力的差別與製程/結構上的優缺點比較。最後，也提出一個保護環製程方法，進一步阻隔雜訊，達到有效利用三維積體電路面積的目標。

In recent years, the improvement of the semiconductor technology have been focused on how to effectively use the costly chip area. To accommodate more transistors in a single chip, people try to minimize the size of the transistors for the past few decades. As the channel length minimize to less than ten’s of nano-meter regime, the characteristic of the MOSFET can not be easily controlled. New ways to increase circuit complexity without large chip size are in great demand. One way of doing so is by stacking the semiconductor chips. That is the main idea of the three-dimensional integrated circuit(3DIC). The key of realizing 3DIC is development of “through silicon via”(TSV). TSVs’ are generally composed of long and wide copper lines. This through substrate wires might induced large potential fluctuation in the substrates, leading to much greater substrate noises. In this study, we intend to investigate these additional substrate noise as a results of the TSVs’.
First, the problems of the TSVcoupled noise are outlined. We then discuss the distribution & magnitude of the TSV-coupled under different condition noise using the simulation software. The simulation results help us conclude some general guidelines of designing the TSV layout, guard-ring structures, so that, the chip area can be effective utilized.

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