適用於H.264/AVC之高速CABAC殘值解碼器架構｜國立清華大學博碩士論文庫

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研究生：	張哲銘 Che-MIng Chang
論文名稱：	適用於H.264/AVC之高速CABAC殘值解碼器架構 A Fast Architecture of the CABAC Decoder for Residual Data in H.264/AVC
指導教授：	陳永昌 Yung-Chang Chen
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	中文
論文頁數：	63
中文關鍵詞：	算術編碼
外文關鍵詞：	H.264, CABAC, decoder
相關次數：	點閱：3 下載：0
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H.264/AVC 是目前最新的視訊壓縮規格，相較於先前的壓縮標準，H.264 在傳輸量的節省與編碼失真的控制上都有顯著的改善，尤其在影像的壓縮和網路傳輸的強健性。此外在同樣的影像品質之下，其所需要的位元率相較於MPEG-2 和MPEG-4 分別減少了約60%和40%。因為其優秀的壓縮品質H.264適用於許多不同的應用，例如高畫質VD、數位電視、視訊通話、網路影像串流等等…。
內容自適應性二元算術編碼 (CABAC)是H.264所採用的熵編碼方法之一，且相較於另一種編碼方法能節省約30%的位元率。在本篇論文中，我們提出了一個針對殘值的高速CABAC解碼器。在內容模型化(Context Modeling)方面，我們使用了預先存取和快取器的機制，配合上對內容模型表格的重新整理以及不同語法元素有其對應的快速演算法，我們的架構能準確且快速的獲得所需要的內容模型。在算術解碼方面，這個步驟是整個CABAC解碼器當中最核心的部份，為了縮短其關鍵路徑，我們針對重新正規化(Renormalization)的運算作最佳化，並且對於整個算數解碼的運算順序做重新排列。經由上述的程序後，其關鍵路徑成功的從縮短為，如此能夠明顯的提昇算術解碼的速度。最後，我們提出一個用於決定在管線化程序中何時作內容模型更新的演算法，藉由對解碼出的結果作判斷，能可以確定每次內容模型在正確的時間被更新，而且也能大量減少內容模型更新的次數進而減少對記憶體存取的次數，以避免浪費不必要的執行時間與功率消耗。
我們將上述的設計以Xilinx的多媒體FPGA平台實現，經過邏輯合成與驗證後，結果證明我們的設計能夠到達每個bin只需要一個週期就可以完成，並且使用較少的硬體資源以及在工作頻率也有較好的表現，非常適合作為系統中的一個邏輯核心。

H.264/AVC is the latest video compression standard. It concentrates on video compression and robust transmission support over networks. H.264/AVC could achieve about 60% bit-rate saving over MPEG-2, and about 40% bit-rate saving over MPEG-4 at the same video quality. Because of its high compression efficiency, H.264 attracts high interest for many applications such as High Definition DVD, Digital TV, Digital Camcorders, Internet video streaming, and others. Context-based Adaptive Binary Arithmetic Coding (CABAC) is the entropy coding method used in H.264 main profile. Compare to the Context-based Adaptive Variable Length Coding (CAVLC), CABAC provides a reduction in bit rate about 30%.
In this thesis, we propose a fast architecture of the CABAC decoder for residual data. Because the binary arithmetic decoder is the critical part of the CABAC decoder. We perform twice reordering technique to reduce the critical path of the decoding process. The critical path has been successfully shorten from to . In the context modeling stage we propose the caching and pre-fetch methods so that the update and load of the context models can be performed at the same time. Furthermore, we propose an algorithm that makes sure the update of the context models in the pipelining at the correct time and decrease the accessing times.
As a result, a fast and simple architecture of the CABAC decoder is proposed. Our design is implemented on Xilinx multimedia board that uses less logic elements and the maximum working frequency is 135 MHz. Because of the less device usage and higher working frequency, it is suitable to be an IP core.

Abstract    i
Table of Contents    iii
List of Figures    v
List of Tables    viii
Chapter 1: Introduction    1
1.1    Overview of the H.264/AVC video coding standard    1
1.2    Motivation    1
1.3    Organization for the Thesis    2
Chapter 2: Context-based Adaptive Binary Arithmetic Coding Algorithm    3
    2.1 Basic Concept of CABAC Framework    3
    2.2 Context Modeling    4
    2.3 Binary Arithmetic Coding    7
       2.3.1 Basic Concept of Arithmetic Coding…………………………..……7
    2.3.2 Basic concept of Binary Arithmetic Coding………………………....9
    2.3.3 Adaptive Binary Arithmetic Decoding Coding Process in
CABAC Standard……………………………………………………10
    2.3.4 Probability Estimation in CABAC……………………………….…13
    2.3.5 The decoding process in CABAC system…………………………..14
    2.4 Debinarization    .....16
       2.4.1 The Unary Code Method……………………………………….…..16
    2.4.2 The Truncated Unary (TU) Method………………………………...16
    2.4.3 The k-th Order Exp-Golomb (UEGk) Method……………………...16
    2.4.4 Fixed-Length (FL) Method………………………………………….18
    2.4.5 The Pre-defined Table Mapping Method……….…………………..18

Chapter 3: Proposed Context-Based Adaptive Binary Arithmetic Decoder architecture…………………….……………..21
3.1.    Flow of the Decoding Process for the Residual Data    21
3.2  Algorithm and architecture of Context modeling    23
     3.2.1 Significance map    23
         3.2.2 Level information...……………………..………………………31
            3.2.3 Architecture of Context Model Memory and Context Model Cache……………………………………………………...…….35
3.3  Architecture of binary arithmetic decoder……………………………..38
    3.4  Archtecture of Debinarization Process……………………………... …46
    3.5  Proposed archtecture of the CABAC decoder……………………… …47
Chapter 4: Verification and Simulation Results    …………….55
    4.1 Design Flow and Implementation    55
    4.2 Simulation Verification and Implementation Result    56
    4.3 Comparison of Related Work    57
Chapter 5: Conclusions and Future Works    58
     5.1 Conclusions    58
     5.2 Future works    58
References    59

                                

[1] Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264 | ISO/IEC 14496-10 AVC).
[2] "JM10.2 Test Model CODEC," ISO/IEC MPEG and ITU-T VCEG Joint Video Team, http://bs.hhi.de/~suehring/tml/, 2005.
[3] J. Ostermann, J. Bormans, P. List, D. Marpe, M. Narroschke, F. Pereira, T. Stockhammer, and T. Wedi, "Video Coding with H.264/AVC: Tools, Performance and Complexity," IEEE Circuits and Systems Magazine, vol. 4, pp. 7-28, 2004.
[4] Detlev Marpe, Heiko Schwarz, and Thomas Wiegand, “Context-Based Adaptive Binary Arithmetic Coding in the H.264/AVC Video Compression Standard”, presented at ICIP, Barcelona, Spain,Sept.2003
[5] S. Saponara, C. Blanch, K. Denolf, and J. Bormans, “The JVT advanced video coding standard: Complexity and performance analysis on a tool-by tool basis,” Packet Video Workshop (PV’03), Nantes, France, April 2003.
[6] J.W. Chen, C.R. Chang, Y.L. Lin, “A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC,” in Proc. IEEE ISCAS, pp.4525-4528, May 2005.
[7] H. Eeckhaut, M. Christiaens, D. Stroobandt and V. Nollet, “Optimizing the critical loop in the H.264/AVC CABAC decoder” DESICS, IMEC, Kapeldreef 75, Leuven, Belgium, Junes, 2006.
[8] Xilinx, “Virtex-II Platform FPGA User Guide”, UG002 (v1.4) 1 November 2002.
[9] Xilinx, “Platform Specification Format Reference Manual”, UG131 (v1.0) August 20, 2004.
[10] J. L. Nunez-Yanez, V. A. Chouliaras, D. Alfonso, F.S.Rovati, “Hardware Assisted Rate Distortion Optimization with Embedded CABAC Accelerator for the H.264 Advanced Video Codec,” IEEE Transactions on Consumer Electronics, MAY 2006.
[11] Stratix Device Handbook, Altera, Jan 2006. [Online]. Available: http://www.altera.com/literature/lit-stx.jsp.
[12] Stratix II Device Handbook, Altera, April 2006. [Online]. Available:
http://www.altera.com/literature/lit-stx2.jsp.

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