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研究生： 金峻暘
Jin, Jun-Yang.
論文名稱： 考慮單元最大負載電容的繞線提升技術的2.5D積體電路拆分製造上的雙重安全防禦方法
A Doubly Secure Defense Approach on 2.5D IC Split Manufacturing considering Cell Max Load Capacitance and Wire Lifting Technique
指導教授： 麥偉基
Mak, Wai-Kei
口試委員: 王廷基
Wang, Ting-Chi
陳宏明
Chen, Hung-Ming
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年： 2021
畢業學年度： 109
語文別： 英文
論文頁數： 29
中文關鍵詞： 最大負載電容 、拆分製造 、繞線提升技術
外文關鍵詞： max load capacitance, split manufacturing, wire lifting
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    • 2.5D IC 的分離製造代表著前端與後端分別在不同的晶圓廠做製造以防止智財權遭到竊取。我們知道在不信任晶圓廠的攻擊者會嘗試去利用自己手上的前段元件來猜測並且攻擊那些後端的繞線。在以往攻擊2.5D IC的方法中，ML base proximity attack 收集了許多不同的特徵且運用機器學習的方法來幫助攻擊者提高恢復的準確率。在此篇論文中，我們首先在舊有的ML-based attack 加上一些新的特徵來改善攻擊的準確率。在所有測試資料中，我們得到平均3.11\% 的改善幅度。再來，我們提出了一個方法來防禦這個改善過後的ML-based attack。受到\cite{concerted wire lifting}的啟發，我們提出一個wire lifting的方法，而且使用該論文中的所提出之elevating cells來幫助我們達到wire lifting的效果。首先，我們對每個inter-die via所連接的cell計算出一個lift score。再來，根據lift score的高低進行排序，取出1\%的cell且將其所有的訊號線都lift到後端去。在實驗結果中顯示出，我們的方法相較於沒有套用任何方法可以平均降低10\%的攻擊準確率。

    The split manufacturing of 2.5D IC delegates the front-end-of-line (FEOL) and back-end-of-line (BEOL) parts to different foundries to prevent IP piracy. We know that attackers in untrusted foundries will attempt to guess the missing connections by its FEOL layout. The state-of-the-art attack method against split manufacturing of 2.5D IC is an ML-based proximity attack. The attack collects various features and uses machine learning to help attackers achieve a higher recovery rate. In this work, we first added some new features to improve the existing ML-based attack \cite{analysis split manufacturing}. We got a 3.11\% accuracy improvement on average among all test cases. Next, we proposed a method to defend against the improved ML-based attack. Inspired by \cite{concerted wire lifting}, we proposed a wire lifting method and applied elevating cells to achieve the wire lifting effect. First, we calculate a lift score for each inter-die sink via's corresponding cell, we called it a candidate cell. Then sort all of them according to their lift scores. Finally, each test case will lift all signal wires of a fixed amount of the sorted candidate cells to BEOL. The experimental results show that our method can decrease the attack accuracy by 10\% for each case compared to the baseline.

    誌謝 ii 摘要 iii Abstract iv Contents v List of Figures vii List of Tables viii 1 Introduction 1 1.1 Hardware Security in advanced technology node 1 1.2 Related Works 2 1.3 Motivation and Contribution 3 1.4 Organization 5 2 Preliminaries 6 2.1 2.5D IC architecture 6 2.2 Generate Unprotected layout 7 2.2.1 Partition 7 2.2.2 Preprocessing 7 2.2.3 Split circuit and signal assignment 8 2.2.4 Placement and routing 8 2.3 Problem formulation 8 3 Machine Learning Framework 10 3.1 Feature Extraction and New Features 11 3.1.1 Feature extraction 11 3.1.2 Observation of new features 12 3.2 Generate Samples and Training and Testing stage 13 4 Wire Lifting Framework 16 4.1 Strategy for wire lifting 17 4.1.1 Construct Manhattan Circle 18 4.1.2 Calculate candidate cell lift score 18 4.1.3 Lift candidate cell nets 18 4.2 Insert Elevating Cells 19 4.2.1 Design for Elevating Cells 19 4.2.2 Insert Elevating Cells Flow 19 4.2.3 Chapter Conclusion 21 5 Experimental Results 22 5.1 Experimental Setup 22 5.2 Comprehensive comparison between new added features 23 5.3 Comparison our wire lifting method with baseline test case 25 6 Conclusion 27 Reference 28

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