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研究生: 張益壽
Yi-Shou Chang
論文名稱: 可變增益之1V互補式金氧半射頻前端電路於無線網路的應用
An 1V CMOS RF Front-End with Variable Gain for WLAN Applications
指導教授: 柏振球
Jenn-Chyou Bor
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2006
畢業學年度: 95
語文別: 中文
論文頁數: 118
中文關鍵詞: 1V互補式金氧半射頻前端電路無線網路可變增益
外文關鍵詞: 1V, CMOS RF Front-End, WLAN, Variable Gain
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  • 本論文中,一個應用於無線網路的低功率與低電壓射頻前端電路和另一個普通功率射頻前端電路會被呈獻。在第一個設計中,它使用了摺疊疊接式的架構來完成低電壓的操作。基於理論與模擬層面的分析,在功率耗率與電路效能之間的取捨就可以找到一個最好的結果。整個電路是在TSMC 0.18 μm的製程下設計與實現。模擬的結果顯示出輸入端反射係數小於-10 dB包涵所要的頻寬(5.15 GHz到5.35 GHz)。 整體的電壓增益為28.1 dB和23.3 dB。整體的雜訊指數為6.12 dB在10 MHz這個頻率上,而10 MHz頻寬內的平均雜訊指數為9.42 dB。電路的功率消耗為5.68毫瓦而且操作在1V的電壓下。P1dB為-23.79 dBm,IIP3為-18.01 dBm。面積佔1.270 * 1.423 mm2。

    在第二個設計裡,射頻前端電路有著寬鬆的設計規格,它不需操作在低功率之下。在較好的條件下設計,因此它可以達到較好的效能。整個電路是在TSMC 0.18 μm的製程下設計與實現。模擬的結果顯示出輸入端反射係數小於-10 dB包涵所要的頻寬。 整體的電壓增益為26.7 dB和15.8 dB,有9 dB的增益範圍。整體的雜訊指數為3.72 dB在10 MHz這個頻率上。P1dB為-20.82 dBm,IIP3為-8.27 dBm。電路的功率消耗為25.56毫瓦而且操作在1.8V的電壓下。面積佔1.303 * 1.451 mm2。


    In this thesis, a RF front-end circuit which has low power consumption and low supply voltage for wireless LAN applications and another RF front-end with normal power consumption are presents. In the first design, it uses the folded-cascoded architecture to achieve low-voltage operation. Based on the theoretic and simulation analysis, the trade-off between the power consumption and circuit performance is conducted. The overall circuit is designed and implemented in TSMC 0.18 μm process. The simulation results show that RF front-end has S11 small than -10 dB during the wanted bandwidth (5.15 GHz to 5.35 GHz). The conversion voltage gain has 28.1 dB and 23.3 dB. The double side band noise figure is 6.12 dB at 10 MHz and average noise figure is 9.42 dB within 10 MHz. The power consumption is 5.68 mW and it operates with 1V supply voltage. P1dB is -23.79 dBm and IIP3 is –18.01 dBm. The overall area is 1.270 * 1.432 mm2.

    In the second design, the RF front-end circuit has normal design specification. It doesn’t operate with low power consumption. So the performance is better then first one. The overall circuit is designed and implemented in TSMC 0.18 μm process. The simulation results show that front-end has S11 small than -10 dB during the wanted band. The conversion gain is 26.7 dB and 15.8 dB and it has about 9 dB gain range. The noise figure is 3.72 at 10 MHz. P1dB is -20.82 dBm and IIP3 is -8.27 dBm. The power consumption is 25.56 mW and it operates with 1.8 V supply voltage. The die area is 1.303 * 1.451 mm2.

    Chapter 1 Introduction 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Analysis of Radio Frequency Front-end System 2.1 Standards of Wireless LAN 4 2.2 Receiver Architecture 6 2.2.1 Homodyne Receiver 6 2.2.2 Super Heterodyne Receiver 7 2.3 System Specifications 8 2.3.1. Noise Figure 8 2.3.2 1dB Gain Compression Point 10 2.3.3 Third Order Harmonic Intercept Point 10 2.3.4 Second Order Harmonic Intercept Point 11 2.3.5 Design Desired Specification 11 Chapter 3 Design of Low Power and Low Voltage (1V) RF Front-End 3.1 Design of Low Noise Amplifier 13 3.1.1 Architecture of LNA 13 3.1.1.1 Common-Gate Architecture 14 3.1.1.2 Common-Source Architecture 15 3.1.1.3 Source Inductive Degeneration for Input Impedance 16 3.1.1.4 Technique of Fully-Differential and Isolation Cascode Mos 18 3.1.2 Noise Model of MOS Transistor 19 3.1.2.1 Thermal Noise 20 3.1.2.2 Gate Noise 20 3.1.2.3 Drain Current Noise 22 3.1.2.4 Flicker Noise 22 3.1.3 Design of LNA with Low Power 23 3.1.3.1 Variable Gain Technique 24 3.1.3.2 Optimization of NF and Power Consumption 25 3.1.4 Design and Simulation Results 32 3.1.5 Summary 43 3.2 Design of Down Conversion Mixer 43 3.2.1 Architecture of Active Mixer 43 3.2.1.1 Theoretical analysis 44 3.2.1.2 Modified Mixer 46 3.2.2 Design and Simulation Results 47 3.2.3 Quadrature Phase Signal 50 3.2.3.1 Design of Poly Phase Filter 52 3.2.3.2 Simulation Results of Poly Phase Filter 52 3.2.4 Summary 53 Chapter 4 Design of RF Front-End for IEEE WLAN 802.11a 4.1 Design of Low Noise Amplifier 55 4.1.1 The Modified LNA Architecture 55 4.1.2 Design and Simulation Results 56 4.1.3 Summary 61 4.2 Design of Down Conversion Mixer 61 4.2.1 Modified Mixer 61 4.2.2 Design and Simulation Results 62 4.2.3 Qradrature Phase Signal 65 4.2.4 Summary 65 Chapter 5 Implementation of Design and Measurement Results 5.1 Results of 1V CMOS RF Front-End 66 5.1.1 RF Front-end Simulation Results 67 5.1.2 Layout Overview 72 5.1.3 PCB layout 74 5.1.4 Measurement Results 80 5.1.5 EM simulation 87 5.2 Results of RF Front-End for IEEE WLAN 802.11a 88 5.2.1 RF Front-end Simulation Results 88 5.2.2 Layout Overview 95 5.2.3 Measurement Results 96 5.2.4 Summary 99 Chapter 6 Conclusion and Future Work

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