隨著電子計算機在人工智慧與物聯網應用中的普及，數據處理量顯著增加，導致系統面臨馮紐曼瓶頸。為了減少數據搬運時間，記憶體內運算成為一個關鍵解決方案。以氧化鉿為基底的鐵電記憶體，由於其高密度、高速讀寫和低功耗等優勢，被認為是實現記憶體內運算的理想選擇。
本研究採用高遷移率材料矽鍺與傳統電晶體的通道材料矽進行週期性磊晶，形成的超晶格異質結構，作為鐵電非揮發性記憶體之通道。通過利用矽鍺與矽之間晶格常數差異產生的應變效應與量子效應，能進一步提升記憶體元件之特性表現。
本研究首先比較了傳統矽和矽鍺/矽超晶格結構作為鰭式鐵電非揮發性記憶體的通道。矽鍺/矽超晶格結構結合高遷移率材料矽鍺以及超晶格異質結構所形成的量子效應，提升鐵電記憶體之操作速度與記憶窗口，並實現多位元操作，有效增進了鐵電非揮發性記憶體的電性表現。
接續以上研究，將矽鍺/矽超晶格通道結構應用於環繞式閘極鐵電非揮發性記憶體。結合高介電常數之氧化鉿/氧化鋯進行超晶格堆疊(SL HZO)作為其閘極氧化層，製作了N型與P型元件。由於環繞式閘極結構具備更佳的閘極控制能力，可降低鐵電非揮發性記憶體之操作電壓，尤其在P型元件中更為顯著，使用± 2 V、100 ns的脈衝電壓即可獲得2.5 V的記憶窗口；而在N型元件中，使用± 4.5 V、100 ns的脈衝電壓可獲得2.25 V的記憶窗口，相較於前一部分所討論之鰭式鐵電非揮發性記憶體，具有更低的操作電壓。值得一提的是，由於P型元件操作電壓較低，其耐用度可達到107次循環、耐久度可達104秒以上，並仍保持極佳的元件特性。
總結而言，使用矽鍺/矽超晶格通道結構結合高介電常數之超晶格氧化鉿鋯閘極氧化層的鐵電非揮發性記憶體展示了出色的電性表現和可靠度，能進行多位元操作，並與現今CMOS製程相容，在實現記憶體內運算方面具有極高的潛力。

With the proliferation of computers in artificial intelligence and Internet of Things (IoT) applications, the volume of data processing has significantly increased, leading to the von Neumann bottleneck. To reduce data transfer time, in-memory computing has become a critical solution. FeFET based on HfO2 are considered ideal for implementing in-memory computing due to their high density, high speed, and low power consumption.
This study employs periodic epitaxy of high-mobility material SiGe and Si as channel materials to form super-lattice heterostructures, serving as the channels for FeFET. By leveraging the strain effect resulting from the lattice constant differences between Si and SiGe, a quantum effect is created, further enhancing the operational speed of the devices.
Initially, this study compared the use of Si and SiGe/Si super-lattice structures as channels for Fe-FinFET. The SiGe/Si super-lattice structure, combining the high mobility of SiGe and the quantum effect from the super-lattice heterostructure, improved the operational speed and memory window of FeFET, enabled multi-bit operation, and effectively enhanced the electrical performance of FeFET.
Building on the previous research, the SiGe/Si super-lattice channel structure was applied to Fe-GAAFET. By integrating high dielectric constant (high-κ) HfO2/ ZrO2 super-lattice stacks (SL HZO) as the gate oxide, N-type and P-type devices were fabricated. Due to the superior gate control capability of the GAA structure, the operating voltage of FeFET was reduced, particularly in P-type devices, where a ± 2 V, 100 ns pulse voltage achieved a memory window of 2.5 V. In N-type devices, a ± 4.5 V, 100 ns pulse voltage achieved a memory window of 2.25 V, indicating a lower operating voltage compared to the Fe-FinFET discussed earlier. Notably, the P-type device demonstrated endurance up to 107 cycles and retention exceeding 104 seconds while maintaining excellent device characteristics due to the lower operating voltage.
In summary, FeFET using SiGe/Si super-lattice channel structure combined with SL HZO as oxide gate oxide demonstrates outstanding electrical performance and reliability, enabled multi-bit operation, and was compatible with current CMOS processes, demonstrating high potential for in-memory computing applications.

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