研究生: |
楊燿聰 Yang, Yao-Tsung |
---|---|
論文名稱: |
高效能的多物件偵測研究與硬體實現 Study of Efficient Multiple Object Detection and Hardware Implementation |
指導教授: | 邱瀞德 |
口試委員: |
范倫達
張添烜 |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 通訊工程研究所 Communications Engineering |
論文出版年: | 2013 |
畢業學年度: | 101 |
語文別: | 英文 |
論文頁數: | 56 |
中文關鍵詞: | 多物件偵測演算法 、多物件概論提高樹 、多物件可行性階層 、低記憶體花費 、高準確性 、漸進式階層演算法 |
外文關鍵詞: | Multiple Object Detection Algorithm, Multiple Object Probability Boosting Tree, Multiple Object Capable Cascades, Low Memory Cost, High Accuracy, Boosted Cascade algorithm |
相關次數: | 點閱:3 下載:0 |
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本篇論文研究多物件偵測演算法進而提出改進方法。目的為提升多物件偵測法的準確性及降低所花費的記憶體。針對多物件概率提高樹演算法,我們利用樹節點索引法降低記憶體花費,與利用漸近式階層取代達到高準確性。再者針對多物件可行性階層演算法,我們利用簡化多物件可行性階層的架構,減少弱分類器的個數以及達到高準確性。利用MIT CBCL汽車資料庫,比較以上所有演算法的記憶體花費以及準確性後,簡化多物件可行性階層演算法有效地減少13.161x103 ~ 261.477x103位元的記憶體以及達到高偵測率95.54%與低假陽性率1.94%。
在多物件漸進式階層演算法的硬體實現,運算積分影像時利用積分窗口減少儲存積分影像的記憶體大小。接著利用平行階層偵測的架構減少偵測時間。此設計晶片核心電路面積1.21mm2並且達到工作頻率100MHz以及30fps速度於處理大小160x120的圖片。
In this thesis, we study the multiple object detection algorithms and propose improved methods. The goal is to increase detection rate and reduce memory cost in multiple object detection methods. For the multiple object probability boosting tree scheme, we use tree node index to reduce memory cost and use boosted cascade to achieve high detection rate and low false positive rate. Furthermore, in multiple object capable cascade method, we propose the single stage cascade to replace the original parallel cascade structure to reduce the number of weak classifier and achieve high accuracy. For MIT CBCL car database, the multiple object capable cascades algorithm with single stage cascade structure reduces low memory cost by around 13.161x103 ~ 261.477x103 bits and achieves high detection rate of 95.54% and low false positive rate of 1.94% compared to above other algorithms.
In the hardware implementation of multiple object boosted cascade scheme, we design an efficient the integral window to reduce the memory cost and calculate feature value. In cascade detection, we reduce the number of weak classifiers storage, and we exploit the parallel cascade detection architecture to reduce the detection time. The post-layout chip achieves operation frequency of 100MHz, processing images of 30 fps with size 160x120, and with core area of 1.21 mm2.
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