本次設計以CMOS影像感測器(CMOS Image Sensor, CIS)後端之類比數位轉換器(Analog to Digital Convertor, ADC)為應用目標，設計一個具有12位元有效位數(Effective Number of Bits, ENOB)、一百千赫茲(100 kHz)頻寬、取樣頻率為一千萬赫茲(10 MHz)之類比數位轉換器電路，同時功率消耗控制在微瓦(micro Watt)等級。
本論文在ADC架構上採用的是連續漸進式類比數位轉換器(Successive Approximation ADC, SAR ADC)，然而多位元數之連續漸進式轉換器最主要的缺點就是電容面積容易過大，因此本論文利用了 passive noise shaping的方式在10位元SAR ADC的結構上實施雜訊重塑，有效提升ADC的ENOB到12 bits，不只更能降低功耗也更省面積。相較主動雜訊調變，被動雜訊調變之優勢為其架構簡單，且主要使用被動元件，不須額外偏壓電路供放大器使用。此外，ADC內部雜訊會造成比較錯誤，因此本論文加入數位錯誤校正電路，能有辦法用一個演算法修正數位輸出的位元。
本論文電路是在 TSMC 0.18 μm 1P6M CMOS製程下實現，晶片總面積包含TSMC的 ESD I/O pad為0.88 mm2，此類比數位轉換器的供應電壓為1.8 V、取樣頻率10 MHz。當訊號背景為輸入 129.39 kHz 的正弦波時，訊號對雜訊及失真比（SNDR）以及有效位元數（ENOB）的模擬結果分別是 86 dB 以及 14-bit，而平均功耗的結果為962 μW。在量測結果中，整體晶片(包括驅動電路)共消耗1723 μW。在頻寬為312.5 kHz情況下有效位數為10.62位元，若縮減頻寬至156.25 kHz，則有效位數可達12.1位元。

The design focuses on the analog-to-digital converter at the backend of the CMOS Image Sensor (CIS) as its application target. It aims to design an ADC circuit with 12-bit Effective Number of Bits (ENOB), 100 kHz bandwidth, and a sampling frequency of 10 MHz, while keeping the power consumption at micro Watt level. The paper adopts a Successive Approximation ADC (SAR ADC) architecture for the ADC design. However, the main drawback of the multi-bit successive approximation converters is the tendency for the capacitor area being too large. Therefore, this paper utilizes passive noise shaping to implement noise shaping in the structure of the 10-bit SAR ADC, effectively increasing the ADC's ENOB to 12 bits. This not only reduces power consumption but also saves area. Compared to active noise modulation, passive noise modulation has the advantages of the simpler structure and primarily using passive components without additional bias circuits for amplifiers. Furthermore, since internal noise in ADCs can cause quantization errors, this paper adds a digital error correction circuit, which can correct the digital output using an algorithm. The circuit is implemented in the TSMC 0.18 μm 1P6M CMOS process, with the total chip area including TSMC's ESD I/O pad being 0.88 mm2. The supply voltage for the ADC is 1.8 V, and the sampling frequency is 10 MHz. Simulation results with the input signal of a 129.39 kHz sine wave show a Signal-to-Noise and Distortion Ratio (SNDR) of 86 dB and an ENOB of 14 bits. The average power consumption is 962 μW. In the measurement results, the overall chip (including driver circuit) consumes a total of 1723 μW. At a bandwidth of 312.5 kHz, the effective number of bits is 10.62 bits. Reducing the bandwidth to 156.25 kHz increases the effective number of bits to 12.1 bits.

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