隨著近年來半導體產業的迅速發展，可攜帶的個人化電子裝置變得十分普及，加上物聯網( Internet of Things )的逐漸興起，大量的資料存取需求使得非揮發性記憶體( Nonvolatile Memory, NVM )所扮演的角色有愈來愈重要的趨勢。而非揮發性記憶體能相容於一般邏輯製程，與積體電路整合於同一塊的晶片上，使得電子產品更加輕薄、體積更小。其中，一次性寫入記憶體憑著低功耗、高可靠性，擁有絕佳的優勢並且廣泛應用於生活中。
本篇論文研究P型非揮發性相容於鰭式電晶體之一次性寫入(One-Time Programmable, OTP)記憶體元件，其相容於一般的邏輯製程，不須增加額外的光罩。此元件是由兩個P型的鰭式電晶體串聯而成，利用閘極介電層硬崩潰作為資料寫入方式，寫入前後的電流差異可得到超過十萬倍的讀取電流比。並且藉由長時間連續讀取以及長時間高溫烘烤測試得知其具有優異的資料保存能力以及干擾抵抗性，使其可以當作先進邏輯非揮發性記憶體來應用。
P型鰭式電晶體之一次性寫入(One-Time Programmable, OTP)記憶體元件擁有功耗低、可靠度高、無須多餘光罩並且可完全相容於16奈米高介電係數金屬閘極(high-κ metal gate, HKMG) CMOS之邏輯製程中、讀取窗大、具微縮潛力等優點，在SL讀取電壓相同的情況下與N型記憶元相比，P型鰭式一次性寫入記憶體能有更長的元件生命週期，因此可視為發展性極高的一次性寫入記憶體。

With the rapid development of the semiconductor industry in recent years, portable electronic products become pervasive in modern life. Considering more and more application by Internet of Things, demands on data storage gradually makes the role of nonvolatile memory (NVM) important. Logic NVMs compatible to CMOS logic process, can be easily embedded into the integrated circuits within a chip. The integration enables electronic products become lighter and compact. One-Time Programmable (OTP) memories with the benefits of low power and high reliability have been widely used in our life.
In this research, we investigate the P-type nonvolatile OTP memory cell based on FinFET technology. It is compatible to 16nm CMOS logic process without extra process or masking step. The memory cell, composed of two standard core FinFET transistors in series, uses the breakdown of high-κ gate dielectric layer as the programming mechanism for data storage. After programming, it demonstrates more than five orders on/off read current ratio. Moreover, the superior data retention and disturbs immunity of P-type OTP are verified by a long-term continuous read and baking under a high temperature. A P-type OTP NVM cell has the advantage of low power consumption, high reliability, large on/off read window and great potential on scaling down. When SL read voltages are the same, P-type OTP has a longer lifetime compared to N-type OTP. With these excellent properties, this memory cell can be viewed as logic non-volatile memory solution for advanced CMOS circuits.

[1] Kilopass Technology Inc. 2015, “Comparison of Embedded Non-
Volatile Memory Technologies and Their Applications.” [ONLINE]
Available at: http://www.kilopass.com/wpcontent/uploads/2010/04/c-
omparison_of_embedded_nvm.pdf [Accessed 3 May 2017].
[2] J. Z. Peng, "Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric," US Patent # US 6667902 B2, 2003.
[3] J. Peng, G. Rosendale, M. Fliesler, et al., "A Novel Embedded OTP NVM Using Standard Foundry CMOS Logic Technology," in Non-Volatile Semiconductor Memory Workshop, 2006, pp. 24-26.
[4] W. Kurjanowicz, "Split-channel antifuse array architecture," US Patent # US 20080038879 A1, 2008.
[5] R. S.-J. Shen, M.-Y. Wu, H.-M. Chen, et al., "A high-density logic CMOS process compatible non-volatile memory for sub-28nm technologies," in VLSI Technology, Symposium on , 2014, pp. 1-2.
[6] C. Kothandaraman, S. K. Iyer, and S. S. Iyer, "Electrically programmable fuse (eFUSE) using electromigration in silicides," Electron Device Letters, IEEE, vol. 23, no.9, 2002, pp. 523-525.
[7] R. S. C. Wang, R. S. J. Shen, and C. C. H. Hsu, "Neobit® - high reliable logic non-volatile memory (NVM)," in Physical and Failure Analysis of Integrated Circuits, 2004, pp. 111-114.
[8] C. S. Yang, S. J. Shen, and C. H. Hsu, "Single poly UV-erasable programmable read only memory," US Patent # US6882574 B2, 2005.
[9] C. C. H. Hsu, Y. T. Lin, and S. J. Shen, "Future prospective of programmable logic non-volatile device," in ASSCC 2006 IEEE Asian, 2006, pp. 35-37.
[10] S. Mittal, S. Gupta, A. Nainani, M. C. Abraham, K. Schuegraf, S. Lodha, U. Ganguly, “Epi defined (ED) FinFET: An alternate device architecture for high mobility Ge channel integration in PMOSFET,” in Nanoelectronics Conference, 2013, pp. 367 – 370.
[11] W.-C. Lee, T.-J. King, and C. Hu, "Evidence of hole direct tunneling through ultrathin gate oxide using P/sup +/ poly-SiGe gate," Electron Device Letters, IEEE, vol. 20, no.6, 1999, pp. 268-270.
[12] Y.-C. Yeo, T.-J. King, and C. Hu, "MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations," Electron Devices, IEEE Transactions on, vol.50, no.4, 2003, pp.1027-1035.
[13] R.H. Fowler and L. Nordheim, “Electron emission in intense electric fields,” Proceedings of the Royal Society of London, Series A 119, 173 (1928).
[14] M. Lenzlinger and E. H. Snow, "Fowler-Nordheim tunneling into thermally grown SiO2," Electron Devices, IEEE Transactions on, vol.15, no.9, 1968, pp. 686.
[15] J. Wu, L. F. Register, and E. Rosenbaum, "Trap-assisted tunneling current through ultra-thin oxide," in Reliability Physics Symposium Proceedings, 1999, pp. 389-395.
[16] Eli Harari, "Dielectric breakdown in electrically stressed thin films of thermal SiO2," Journal of Applied Physics, vol. 49, no.4, 1978, pp.2478-2489.
[17] S. A. Sahhaf, R. Degraeve, P. J. Roussel, et al., "TDDB Reliability Prediction Based on the Statistical Analysis of Hard Breakdown Including Multiple Soft Breakdown and Wear-out," in Electron Devices Meeting, 2007, pp. 501-504.
[18] A. Berman, "Time-Zero Dielectric Reliability Test by a Ramp Method," in Reliability Physics Symposium, 1981, pp. 204-209.
[19] J. McPherson, J.-Y. Kim, A. Shanware, et al., "Thermochemical description of dielectric breakdown in high dielectric constant materials," Applied Physics Letters, vol. 82, 2003, pp. 2121-2123.
[20] J. W. McPherson and H. C. Mogul. "Underlying physics of the thermochemical E model in describing low-field time-dependent dielectric breakdown in sio2 thin films," Journal of Applied Physics, vol. 84, 1998, pp. 1513-1523.
[21] I.-C. Chen, S. E. Holland, and C. Hu, "Electrical breakdown in thin gate and tunneling oxides," Electron Devices, IEEE Transactions on, vol. 32, 1985, pp. 413-422.
[22] R. Degraeve, G. Groeseneken, R. Bellens, et al., "A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides," in Electron Devices Meeting, 1995, pp. 863-866.
[23] K. Okada, W. Mizubayashi, N. Yasuda, et al., "Model for dielectric breakdown mechanism of HfAlOx/SiO2 stacked gate dielectrics dominated by the generated subordinate carrier injection," in Electron Devices Meeting, 2004, pp. 721-724.
[24] H. Satake and A. Toriumi, "Dielectric breakdown mechanism of thin-SiO2 studied by the post-breakdown resistance statistics," Electron Devices, IEEE Transactions on, vol. 47, 2000, pp. 741-745.
[25] B.-H. Lee, C.-Y. Kang, P. Kirsch, et al., "Electric-field-driven dielectric breakdown of metal-insulator-metal hafnium silicate," Applied Physics Letters, vol. 91, 2007, pp. 243514.
[26] W. –Y. Hsiao, P. -C. Peng, T. -S Chang, et al., “A New High-Density Twin-Gate Isolation One-Time Programmable Memory Cell in Pure 28-nm CMOS Logic Process,” Electron Devices, IEEE Transactions on, vol. 62, 2014, pp. 121-127.
[27] N. Rahim and D. Misra, "Temperature Effects on Breakdown Characteristics of High-k Gate Dielectrics with Metal Gates," Device and Materials Reliability, IEEE Transactions on, vol.8, 2008, pp.689-693.
[28] N. Rahim and D. Misra, "Breakdown Characteristics of High-k Gate Dielectrics with Metal Gates," ECS Transactions, vol. 13, 2008, pp.91-97.
[29] R. Moonen, P. Vanmeerbeek, G. Lekens, et al., “Study of Time-Dependent Dielectric Breakdown on Gate Oxide Capacitors at High Temperature,” in Physical and Failure Analysis of Integrated Circuits, 2007, pp. 288-291.
[30] J. C. Lee, I.-C. Chen, and C. Hu, "Modeling and Characterization of Gate Oxide Reliability," Electron Devices, IEEE Transactions on, vol. 35, no.12, 1988, pp. 2268-2278.
[31] Dick James, "High-k/metal gates in the 2010s," in SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2014, pp. 431-438.
[32] Dick James, "Moore's law continues into the 1x-nm era," in SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2016, pp. 324-329.
[33] I. C. Chen, S. Holland, K. K. Young, et al., "Substrate hole current and oxide breakdown," Applied Physics Letters, vol. 49, no.11, 1986, pp.669-671.
[34] Koji Eriguchia and Masaaki Niwa, "Temperature and stress polarity-dependent dielectric breakdown in ultrathin gate oxides," Applied Physics Letters, vol. 73, no.14, 1998, pp. 1985-1987.
[35] Piero Olivo, Thao N. Nguyen, and Bruno ricco, "High file induced degradation in ultra-thin SiO2 films," Electron Devices, IEEE Transactions on, vol. 35, no.12, 1988, pp. 2259-2267.
[36] H. C. Lin, D. Y. Lee, C. Y. Lee, et al., "New Insights into Breakdown Modes and Their Evolution in Ultra-Thin Gate Oxide." in VLSI Technology, Systems, and Applications, 2001, pp. 37-40.
[37] L.-Y. Yang, M.-C. Hsieh, J.-S. Liu, et al., "A Highly Scalable Interface Fuse for Advanced CMOS Logic Technologies," Electron Device Letters, IEEE, vol. 33, 2012, pp. 245-247.
[38] E. Hamdy, J. McCollum, S. O. Chen, et al., "Dielectric based antifuse for logic and memory ICs," in Electron Devices Meeting, 1988, pp.786-789.
[39] H. Ito and T. Namekawa, "Pure CMOS one-time programmable memory using gate-ox anti-fuse," in Custom Integrated Circuits Conference, 2004, pp. 469-472.
[40] F. Li, X. Yang, A. T. Meeks, et al., "Evaluation of SiO2 antifuse in a 3D-OTP memory," Device and Materials Reliability, IEEE Transactions on, vol. 4, 2004, pp. 416-421.
[41] C.-E. Huang, H.-M. Chen, M.-B. Chen, et al., "A New CMOS Logic Anti-Fuse Cell with Programmable Contact," in Non-Volatile Semiconductor Memory Workshop, 2007, pp. 48-51.
[42] Y.-H. Tsai, H.-M. Chen, H.-Y. Chiu, et al., "45nm Gateless Anti-Fuse Cell with CMOS Fully Compatible Process," in Electron Devices Meeting, 2007, pp. 95-98.
[43] W. T. Chan, K. P. Ng, M. C. Lee, et al., "CMOS-compatible zero-mask One Time Programmable (OTP) memory design," in Solid-State and Integrated-Circuit Technology, 2008, pp. 861-864.
[44] Z. C. Liu, R. F. Zheng, J. W Sun, "A gate-oxide-breakdown antifuse OTP ROM array based on TSMC 90nm process," in International Symposium on Next-Generation Electronics (ISNE), 2015, pp. 1-3.