長久以來，以快閃記憶體為基底的固態硬碟(NAND flash-based solid-state drives, SSDs) 裡連接快閃記憶體控制器和快閃記憶體晶片的介面都被設計成使用同一速度進行讀取和寫入。然而，因為快閃記憶體天生讀取的速度是寫入的10-20 倍快，此種被廣泛接受使用的架構並不是最佳的。

這篇論文提出並研究使傳輸介面的讀取速度和寫入速度不相等以解決上述問題進而增進固態硬碟的讀取效能。我們將提出的架構稱做非對稱互連架構。此架構建議快閃記憶體或是快閃記憶體控制器的設計者將硬體資源傾注於讀取的部分，相對的，設計者能省下寫入方面的支出。在此，非對稱互連架構並不限定為特定的設計而是一種設計時的概念。為了驗證此架構的可行性，我們使用動態時間校準(dynamic timing calibration, DTC) 的技術將一個現有的對稱互連晶片改為非對稱的形式並將其讀取速度推至極限。晶片的實驗結果顯示使用DTC 後，讀取的速度(200 MHz) 能達到寫入(50 MHz)的4倍，且固態硬碟模擬的結果更顯示讀取效能至多能改善為原本
的1.9倍。

NAND flash-based solid-state drives (SSDs) have long been architected
in the way that the interconnections between a flash controller and the associated flash memory chips operate at a symmetric speed in both directions. However, this commonly accepted and widely used architecture is suboptimal to SSDs because reading flash cells is 10 to 20x faster than writing them.

This thesis proposes and studies desymmetrizing the speed of data interfaces in SSDs to alleviate the aforementioned issue and improve the read performance of SSDs. I name the proposed SSD architecture desymmetrized interconnection (DI) architecture. DI architecture guides flash and controller designers to dedicate hardware resources
and advanced mechanisms to speed up the flash-to-controller direction
but free the designers from the costs and constraints of equivalently
speeding up the other direction. As a proof of concept, I propose
dynamic timing calibration (DTC) techniques to experimentally
turn an existing symmetric data interface into a desymmetrized one
that pushes the flash-to-controller frequency to its limit. Real flash chip experiments show that 4x higher (200 MHz) flash-to-controller frequency than that of the other direction (50 MHz) is achieved using DTC, and SSD simulation results further demonstrate up to 1.9xSSD read response time improvement.

[1] “JESD230C NAND flash interface interoperability.” https://www.jedec.org/standards-documents/docs/jesd230c, Oct. 2016.

[2] “ONFi 4.1 standard.” http://www.onfi.org/specifications, Dec. 2017.

[3] K.-D. Suh, B.-H. Suh, Y.-H. Lim, J.-K. Kim, Y.-J. Choi, Y.-N. Koh, S.-S.Lee, S.-C. Kwon, B.-S. Choi, and J.-S. Yum, “A 3.3 V 32 Mb NAND Flash memory with incremental step pulse programming scheme,” IEEE J. Solid-State Circuits, vol. 30, pp. 1149 –1156, November 1995.

[4] Y. Wang, “Ultra high throughput LDPC schemes for SSD,” in Flash Memory Summit (FMS), 2016.

[5] “ONFi 4.0 standard.” http://www.onfi.org/specifications, Apr. 2014.

[6] “Xilinx ZedBoard FPGA platform.” http://zedboard.org/product/zedboard.

[7] “Advantest V93000 IC test system.” https://www.advantest.com/products/ic-test-systems/v93000-soc-smart-scale.

[8] N. Agrawal, V. Prabhakaran, T. Wobber, J. D. Davis, M. Manasse, and R. Panigrahy, “Design tradeoffs for SSD performance,” in USENIX Annual Technical Conference (USENIX ATC), June 2008.

[9] D. Narayanan, A. Donnelly, and A. Rowstron, “Write off-loading: Practical power management for enterprise storage,” Trans. Storage, vol. 4, pp. 10:1–10:23, November 2008.

[10] K. Zhao, K. S. Venkataraman, X. Zhang, J. Li, N. Zheng, and T. Zhang, “Over-clocked SSD: Safely running beyond flash memory chip I/O clock specs,” in Symposium on High Performance Computer Architecture (HPCA), 2014.

[11] A. Birrell, M. Isard, C. Thacker, and T. Wobber, “A design for highperformance flash disks,” SIGOPS Oper. Syst. Rev., vol. 41, pp. 88–93, April 2007.

[12] A. Gupta, Y. Kim, and B. Urgaonkar, “DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings,” in Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2009.

[13] S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S. Park, and H.-J. Song, “A log buffer-based flash translation layer using fully-associative sector translation,” ACM Trans. Embed. Comput. Syst., vol. 6, July 2007.

[14] H. Cho, D. Shin, and Y. I. Eom, “KAST: K-associative sector translation for NAND flash memory in real-time systems,” in Design, Automation Test in Europe Conference Exhibition (DATE), 2009.

[15] Y. Jin, H.-W. Tseng, Y. Papakonstantinou, and S. Swanson, “KAML: A flexible, high-performance key-value SSD,” in Symposium on High Performance Computer Architecture (HPCA), 2017.

[16] L. M. Grupp, J. D. Davis, and S. Swanson, “The harey tortoise: Managing heterogeneous write performance in SSDs,” in USENIX Annual Technical Conference (USENIX ATC), 2013.

[17] Q. Li, L. Shi, C. J. Xue, K. Wu, C. Ji, Q. Zhuge, and E. H.-M. Shasi, “Access characteristic guided read and write cost regulation for performance improvement on flash memory,” in USENIX Conference on File and Storage Technologies (FAST), 2016.

[18] R.-S. Liu, C.-L. Yang, and W. Wu, “Optimizing NAND flash-based SSDs via retention relaxation,” in USENIX Conference on File and Storage Technologies (FAST), 2012.

[19] Y. Luo, Y. Cai, S. Ghose, J. Choi, and O. Mutlu, “WARM: Improving NAND flash memory lifetime with write-hotness aware retention management,” in Symposium on Mass Storage Systems and Technologies (MSST), 2015.

[20] N. Xie, G. Dong, and T. Zhang, “Using lossless data compression in data storage systems: Not for saving space,” IEEE Trans. Comput., vol. 60, pp. 335–345, 2011.

[21] C. Ji, L.-P. Chang, L. Shi, C. Gao, C. Wu, Y. Wang, and C. J. Xue, “Lightweight data compression for mobile flash storage,” ACM Trans. Embed. Comput. Syst., vol. 16, pp. 183:1–183:18, Sept. 2017.

[22] C.-W. Chang, G.-Y. Chen, Y.-J. Chen, C.-W. Yeh, P.-Y. Eng, A. Cheung, and C.-L. Yang, “Exploiting write heterogeneity of morphable MLC/SLC SSDs in datacenters with service-level objectives,” IEEE Trans. Comput., vol. 66, pp. 1457–1463, Aug 2017.

[23] R.-S. Liu, M.-Y. Chuang, C.-L. Yang, C.-H. Li, K.-C. Ho, and H.-P. Li, “ECCache: Exploiting error locality to optimize LDPC in NAND flash-based SSDs,” in Design Automation Conference (DAC), 2014.

[24] R.-S. Liu, M.-Y. Chuang, C.-L. Yang, C.-H. Li, K.-C. Ho, and H.-P. Li, “Improving read performance of NAND flash SSDs by exploiting error locality,” IEEE Trans. Comput., vol. 65, pp. 1090–1102, April 2016.

[25] T.-Y. Chen, Y.-H. Chang, C.-C. Ho, and S.-H. Chen, “Enabling sub-blocks erase management to boost the performance of 3D NAND flash memory,” in Design Automation Conference (DAC), 2016.

[26] M. Kim, J. Lee, S. Lee, J. Park, and J. Kim, “Improving performance and lifetime of large-page NAND storages using erase-free subpage programming,” in Design Automation Conference (DAC), 2017.