本論文闡述了一個嶄新的電容感測電路架構。其利用了載波輸入MEMS全差動電橋(fully-differential bridge circuit)搭配電壓緩衝器(voltage buffer)作為前級，其能將電容訊號調變至高頻，以避開電路中的低頻雜訊。而後再利用一切換電容的解調電路，將訊號解調回基頻並放大，有效減少因為感測電容不匹配，所造成的解調後訊號之交流失真。在此解調電路中，吾人利用相關雙取樣技巧有效降低電路的低頻雜訊及輸入偏差電壓，增加系統的感測度。設計完成之電路佈局 吾人搭配一微機電加速度感測結構組成系統，委託國家晶片設計中心(CIC)進行下線，製程技術由台灣積體電路公司(TSMC)之0.35um Mixed-Signal 2P4M CMOS提供。由後模擬(post-simulation)得該電路在1fF電容的變化下，解調後訊號之靈敏度為155mV/fF，且在時域模擬上也驗證其抗交流失真能力。下線完成的晶片量測得其電路部分訊噪比(SNR)為44dB，訊噪與失真比(SNDR)為42.7dB，無雜訊動態範圍(SFDR)為36.3dB，與模擬結果相近，展現其良好的線性度。在功率消耗方面，當電路在4MHz的時脈頻率運作時，其值為4.29mW。量測結果也證實該電路在微機電電容不匹配比例最高達到10.6%時，仍能解調並降低交流失真至最低，適合用於微機電電容感測的應用上。

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