With the development of capacitive sensors, capacitive sensor interfaces become more and more important. The values of the capacitance are generally small due to the integration of the sensor and readout circuit on a chip. Therefore delta-sigma modulator is a good solution, which has the advantage of high resolution and is often applied in audio band, to deal with the capacitive sensors in pico-Farad order and varying in low frequency. In addition, switched-capacitor delta-sigma modulator is also insensitive to the parasitic capacitance to ground.

In this thesis, a Capacitance-to-Digital Converter is designed and implemented in CMOS 0.35um 2P4M technology based on delta-sigma modulator architecture. This circuit can be used not only as a CDC (Capacitance-to-Digital Convertor), but also as an ADC (Analog-to-Digital Converter). Simulations and measurements show that a peak SNR of 68dB and a dynamic range of 70 dB are achieved at a sampling rate of 8.2MHz and signal bandwidth of 10KHz under 3V supply voltage.

隨著電容式感測器的發展，電容式感測器介面電路愈顯重要。感測器與讀出電路需整合在單一晶片上，所以電容感測器的電容值通常很小。因此處理一個變異速度慢且小等級(pico-Farad)的電容，使用三角積分調變器是量測電容感測器之良好方法，因為三角積分調變器擁有高解析度且常被應用於音頻，而交換式電容(Switched-Capacitor)三角積分器亦具有對寄生電容不敏感的優點。
本篇論文設計一個電容數位轉換器，並透過國家晶片系統設計中心以TSMC 0.35um 2P4M標準製程來實現完成。此電路在使用上可以當作一個CDC (Capacitance-to-Digital Converter) 也可以是一個ADC (Analog-to-Digital Converter)。模擬及量測顯示在3V供應電壓及8.2MHz的取樣頻率、10KHz的頻寬下，可以得到68dB SNR與70dB 動態範圍。

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