在現代晶片設計中，連線延遲是晶片效能的重要因素。繞線是負責做出實體連線的階段，因此是大型體電路設計中重要的階段。在全域繞線中，典型的繞線器會反覆的使用迷宮繞線演算法試圖得到最佳解。在多數的狀況下，過程中繞線器找到的新路徑的成本若是比舊的路徑差就會被拋棄。在這篇論文，我們試圖去預測繞線器在給定資源與限制下，進行繞線的結果會不會得到比較好的結果。這個問題被視為一個分類問題，將繞線資源轉成影像後，訓練一個卷積神經網路來預測結果。訓練完成後，在C++環境下測試網路來得到最終的結果。我們使用一個學術界的全域繞線器NTHU-Route 2.0執行ISPD08的測資來產生我們的資料集。訓練的模型可以在NTHU-Route 2.0 main stage和refinement stage分別達到78%準確率和85%準確率。模型預測的時間比約略一半的測資繞線所需時間快且在某些測資有顯著的優勢。

Interconnect delay is the major factor of the chip performance in modern design. Routing is responsible for making the physical connection and thus is a crucial step in very large-scale integration (VLSI) design. In global routing, a typical router will use a maze routing algorithm to reroute the congested nets iteratively to approximate the optimal solution. The new path found by the router in this process will in general be abandoned if the path does not have an advantage over the old one. In this thesis, we aim to predict if the router can generate a feasible path under the given routing resources and constrains. The routing resources are transformed into an image and the problem is cast into a classification problem. A convolutional neural network (CNN) is trained to make the prediction. After training, the model is executed under a C++ environment to collect the final results. We extract the datasets from the result of an academic global router NTHU-Route 2.0 on ISPD08 testcases. Our model can reach 78% accuracy on the main stage and 85% accuracy on the refinement stage of NTHU-Route 2.0. The prediction time of our model is faster than the running time of performing maze routing on about half of the testcases and is notably faster on some of the testcases.

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