在晶片匯流排的設計上，串列連結因為克服了多位元之並列連結的訊號干擾、偏移與面積花費的問題而受到了很大的關注。然而，串流多位元並列連結卻會增加位元的切換與功率的消耗。在本篇論文中，我們提出了一個位元反向的編碼架構，與傳統的串流編碼架構相比，其可再省12%的切換。此位元反向的架構很簡單且編碼器與解碼器架構是完全相同的。跟前人提出的切換反向架構相比其需要的邏輯閘個數也較少。但其需要在每個編碼單位後增加一個額外的指示位元來表示此資料已被編碼了。此額外的位元不僅增加了傳輸的負擔也增加了資料的切換次數。我們進而提出了一個遷入的反向編碼架構，其利用了串流資料中時脈與資料的相位差來解決額外指示位元的問題。跟編碼在串流前(ES)架構相比，其可省下31%的資料切換。根據分析與模擬結果，我們所提出的架構在各種不同機率的並列匯流排資料轉串流連結中提供了較低的資料切換。而當匯集成串的資料流增加，資料切換的減低率會變成一常數。此外，增加線與線的空間會減低相鄰線之間產生的的電容。所以，一個最佳的匯集數與最佳的線寬、線與線空間是存在來減小匯流排的能量消耗並增加每面積單位的匯流排輸出量。利用得到最大單位面積輸出的匯集數、線寬與線空間和遷入反向編碼架構，與並列式的匯流排線相比，其可減低75%的功耗。

Serial link interconnect catches lots of attention for on-chip bus design due to its advantages over multi-bit parallel interconnect in terms of crosstalk, skew, and area cost. However, serializing multi-bit parallel bus tends to increase bit transition and power dissipation. In this paper, we propose a bit-revert transition inversion (BTI) coding scheme that can reduce up to 12% transitions compared to the traditional serial-encode (SE) scheme. The BTI coding scheme is simple and exactly the same for the encoder and decoder. The resulting architecture needs less gate count compared to previous transition inversion coding scheme. However, an extra indication bit is added in every codeword to represent inversion occurrence. This extra bit increases the transmission overhead and the bit transitions. We further propose an embedded transition inversion (ETI) coding scheme that uses the phase difference between clock and data in the transmitted serial data to resolve the issue of the extra indication bit. This ETI coding scheme can reduce up to 31% of transition compared with the ES scheme. From our analysis and simulation results, our proposed coding scheme produces low bit transition on the serial link for different kinds of data pattern on the parallel bus. Multiplexing more bit per serial link increases the transition reduction that becomes constant. In addition, increasing the line spacing reduces the coupling capacitance between adjacent lines. Thus, an optimum degree of multiplexing and an optimum width and spacing exist, which minimizes the bus energy dissipation and maximizes the bus throughput per unit area. Using the optimum degree of multiplexing, optimum width and space for maximum throughput per unit area and ETI coding scheme, our proposed scheme reduces 75% energy compared to the parallel bus line.

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