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研究生: 潘欽寒
Chin-Han Pan
論文名稱: 以分子束磊晶成長高介電常數氧化鉿之金氧半電容及金氧半場效電晶體之研究
High-□ MOSCAP and MOSFET with MBE-grown HfO2
指導教授: 吳孟奇
M.C. Wu
郭瑞年
J. Kwo
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2006
畢業學年度: 94
語文別: 英文
論文頁數: 70
中文關鍵詞: 分子束磊晶高介電常數氧化鉿金氧半電容金氧半場效電晶體二段式退火等效氧化層厚度閘極漏電流活化溫度氧化釔原子層沉積
外文關鍵詞: MBE, High-□, HfO2, MOSCAP, MOSFET, two-steps annealing, EOT, gate leakage current, activation temperature, Y2O3, ALD
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  • 本實驗室使用分子束磊晶(MBE)的方法在矽晶片上成長HfO2高介電常數(□ = 15)氧化層,且HfO2與矽晶片之間並無任何的二氧化矽或其它的矽氧化物產生,這是在此領域第一次發現的成果。除此之外,我們利用在Ar/N2的電漿環境中濺鍍鈦的方式來沉積TiN金屬閘極。二段式退火被使用來改善高介電常數金氧半電容(High-□ MOSCAP)的電特性,界面間的能量態密度(Dit)經Terman method計算約為1E12 ev-1cm-2。而TiN/HfO2閘極層之熱穩定性也將在本論文中探討,我們發現元件的閘極漏電流主要是由HfO2的再結晶現象所貢獻的。我們也發現再經較高溫度(600~800oC)退火後,電容值會下降,這表示有一層低介電常數介面層的形成。我們可以使用TiN/Ti/HfO2閘極層來達到較小的等效氧化層厚度(EOT),這層鈦金屬緩衝層能用來提高聚積電容值。為了要提高HfO2的再結晶溫度,我們使用MBE技術來沉積參雜20%Y2O3的HfO2,所參雜的Y2O3造成了活化溫度及介電常數的提升,然後能達到較佳的元件效能。另外,我們已經結合MBE及ALD(原子層沉積)技術來成長HfO2介電質。在成長ALD-HfO2之前,我們先用MBE沉積2 nm 的HfO2襯墊,這是我們首次使用這種方法來成長閘極介電層。如我們所預期,一個擁有此閘極氧化層的金氧半場效電晶體展現了極佳的成果,我們得到了ID = 240 mA/mm 以及 gm (transconductance)=120 mS/mm,這樣的結果大幅地改善了僅用ALD方式成長的元件特性,並與其他主要研究團隊所發表的結果相當。


    In this MS thesis, we employed the molecular beam epitaxy (MBE) method to deposit amorphous HfO2 dielectrics (□ = 15) on silicon. We have demonstrated for the first time an atomically abrupt HfO2/Si interface free of SiO2 or silicate formation. In addition, TiN metal gate was deposited by reactive sputtering from a pure Ti target in Ar/N2 plasma. A two-steps annealing studies were carried out to improve the electrical performance of high-□ gate dielectric MOS capacitors. The interface trap density (Dit) were calculated by Terman method to be 1E12 eV-1cm-2. Furthermore, the thermal stability of TiN/MBE-HfO2 gate stack was studied. We found the gate leakage current could be attributed to the re-crystallization of the HfO2. We also found the capacitance was decreased after higher annealing temperature (600~800oC). It indicated the formation of low-κ interfacial layer. We could use a TiN/Ti/HfO2 gate stake to achieve smaller EOT. The Ti layer acted as a buffer to enhance the accumulation capacitance. In order to increase the re-crystallization temperature of the HfO2, we use MBE technique to deposit the HfO2 doped with 20% Y2O3. The Y2O3 doping leading to increased activation temperature and dielectric constant. Then a better device performance was achieved. Another approach on the dielectric using HfO2 had been carried out by combining MBE and ALD techniques. Prior to ALD-grown HfO2, a template of HfO2 (2nm) was deposited by MBE first. That’s the first time we use this method to grow the gate dielectric. As we expect, a MOSFET with such gate oxide displays excellent results. A ID of 240 mA/mm and gm of 120 mS/mm were attained, which were much better than that of simply ALD-grown case and comparable to the data reported by other major groups.

    Chapter 1: Introduction 1 1.1 Limits to SiO2 scaling 3 1.2 High-k□gate dielectric 4 1.3 Metal gate 7 Chapter 2: Fundamentals of the MOSFET 10 2.1 C-V characteristics of the MOS device 10 2.2 MOSFET I-V characteristics 12 2.3 Defects in the Si/SiO2 system 14 2.4 Tunneling effects 16 Chapter 3: Electrical characterization of MOS structures 19 3.1 Electrical measurement instruments 19 3.2 Physical parameters extracted from C-V curves 24 3.3 Calculations of Interfacial density of state (Dit) 28 3.4 Improved two-frequency method for the MOS capacitor 30 Chapter 4: Experimental procedures 32 4.1 MBE-HfO2 deposition 32 4.2 ALD-HfO2 growth 33 4.3 TiN metal-gate deposition 35 4.4 High-□ MOSCAPs fabrication 36 4.5 High-□ MOSFETs fabrication 37 Chapter 5: Results and discussion 41 5.1 Physical characteristics of high-k□HfO2 41 5.2 The properties of Sputtering TiN films 43 5.3 Electrical properties of MOSCAPs 45 5.4 Electrical properties of MOSFETs 61 Chapter 6: Conclusion 70

    [1] G. E. Moore 1965 Electronics 38 114-117
    [2] International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2001.
    [3] G. Timp et al 1999 Tech.Dig. Int. Electron Devices Meet. (Piscataway: IEEE) p 55
    [4] R. Chau, J. Kavalieros , B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy and G. Dewey 2000 Tech. Dig. Int. Electron Devices Meet. (Piscataway: IEEE) p 45
    [5] M. Depas, B. Vermeire, P. W. Mertens, R. L. Van Meirhaeghe and M. M. Heyns 1995 Solid-State Electron. 38 1465
    [6] S. H. Lo, D. A. Buchanan, Y. Taur and W. Wang 1997 IEEE Electron Dev. Lett. 18 209
    [7] A. T. Fromhold 1981 Quantum Mechanics for Applied Physics and Engineering (New York: Dover)
    [8] E. Merzbacher 1998 Quantum Mechanics (New York: Wiley)
    [9] For review, see G. D. Wilk et al, J. Appl. Phys. 89, 5243, (2001).
    [10] Materials Research Bulletin, March 2002 issue, on “Alternative Gate Dielectrics for Microelectronics”, Ed. by R. M. Wallace and G. D. Wilk.
    [11] L. Kang, B. H. Lee, W. J. Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi and J. C. Lee, 2000 IEEE Trans. Electron Devices, 181
    [12] Wilk G D, Wallace R M and Anthony J M 2001 J. Appl. Phys. 89 5243
    [13] E. Josse, T.Skotnicki 1999 Tech. Digest, Int. Electron Device Meet. (Piscataway: IEEE) pp. 661-664
    [14] J. Y.-C. Sun, C. Wong, Y. Taur, C.-H. Hsu, 1989 Dig. Technical Papers, VLSI Symp. Technology. (Piscataway: IEEE) pp.17-18
    [15] I. De, D. Johri, A. Srivastava, C.M. Osburn, 2000 Solid-State Electron. 44 1077– 1080.
    [16] J.C. Hu, H. Yang, R. Kraft, A.L.P. Rotondaro, S. Hattangady, W.W. Lee, R.A. Chapman, C.-P. Chao, A. Chatterjee, M. Hanratty, M. Chen, I.-C. Chen, 1997 Tech. Dig. Int. Electron Devices Meet. (Piscataway: IEEE) pp. 825– 828.
    [17] Y.-S. Suh, G.P. Heuss, J.-H. Lee, V. Misra, 2003 IEEE Electron Device Lett. 24 439– 441.
    [18] H. Wakabayashi, Y. Saito, K. Takeuchi, T. Mogami, T. Kunio, 2001 IEEE Trans. Electron Devices 48 2363– 2369.
    [19] B. Tavel, T. Skotnicki, G. Pares, N. Carrie`re, F. Leverd, C. Julien, J. Torres, R. Pantel, 2001 Tech. Dig. Int. Electron Devices Meet. (Piscataway: IEEE) pp. 825– 828.
    [20] W.P. Maszara, Z. Krivokapic, P. King, J.-S. Goo, M.-R. Lin, 2002 Tech. Dig Int. Electron Devices Meet.. (IEEE, Piscataway) pp. 367– 370.
    [21] H. Zhong, G. Heuss, V. Misra, 2000 IEEE Electron Device Lett. 21 593–595.
    [22] B.-Y. Tsui, C.-F. Huang, 2003 IEEE Electron Device Lett. 24 153–155.
    [23] B.E. Deal, “Standardized Terminology for Oxide Charges Associated with Thermally Oxidized Silicon”, IEEE Trans. Elec. Dev., vol. ED-27, p. 606, 1980
    [24] Fowler R H and Nordheim L 1928 Proc. R. Soc. A 119 173
    [25] Schuegraf K F and Hu C 1994 IEEE Trans. Electron Devices 41 761
    [26] Gehring A, Grasser T, Kosina H and Selberherr S 2002 J. Appl. Phys. 92 6019
    [27] Nicollian E H and Brews J R 1982 MOS Physics and Technology (New York: Wiley)
    [28] L. M. Terman, “An Investigation of Surface States at a Silicon / Silicon Oxide Interface Employing Metal-Oxide-Silicon Diodes” , Solid-State Electron. 5, 285-299. Sept. /Oct. 1962
    [29] H. T. Lue, C. Y. Liu, and C. Y. Tseng, 2002 IEEE Electron Device Lett. 23, 553
    [30] Mikko Ritala, Kaupo Kukli, Antti Rahtu, Petri I. R□is□nen, Markku Leskel□, Timo Sajavaara, and Juhani Keinonen 2000 Science 288 319 - 321.
    [31] B. Maiti, P. J. Tobin, C. Hobbs, R. I. Hegde, F. Huang, DLO Meare, D. Jovanovic, M. Mendicino, J. Chen, D. Connelly, O. Adetutu, , J. Mogab, J. Candelaria, L. B. La. 1998 Tech. Dig. Int. Electron Devices Meet. (IEEE, Piscataway) p.781
    [32] F. R. Chen, W. G. Lee, Y. J. Lee, M. Hong, and J. Kwo, unpublished
    [33] Dieter K. Schroder, “Semiconductor Material and Device Characterization”, 2nd edition, (New York: Wiley)
    [34] R. Chau et al, IEEE Electron Device Letters, Vol. 25, No. 6, June 2004.

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