本研究探討如何求得一座半導體晶圓廠最適當的在製品存貨總量及其在各工作站與作業站的最適分配方法，以維持在最大產出的情況下達到最低的晶圓製造週期時間。本研究將整廠的在製品存貨分為瓶頸在製品存貨以及非瓶頸在製品存貨兩類，瓶頸在製品存貨與晶圓廠的產出以及整體在製品存貨之間擁有極強的關聯性，因此本研究利用類神經網路從繁瑣的資料中釐清這三者之間的關係，並訂下最適當的量。其次，本研究利用等候理論來探討非瓶頸在製品存貨與晶圓製造週期時間的關係，期望能有效的分配所有的在製品存貨到個別的工作站以及對應之作業站，作為調整整體生產線平衡的基準。最後參考相關文獻中所提出的派工法（MIVS），將本研究所提出的在製品存貨水準代入MIVS中，一方面利用MIVS使晶圓廠的物料流動能維持本研究所提出的在製品存貨水準，另一方面本研究所提出的在製品存貨水準也能夠強化MIVS的效益。
本研究利用模擬法來驗證此在製品存貨水準與MIVS所帶來的效益，結果發現MIVS在套用本研究提出的最適在製品存貨水準後，在相同產出量水準下，製造週期時間的平均值較對照組提昇了16%的效益，而且沒有增加製造週期時間的變異。

The function of WIP for different workstations of a semiconductor manufacturing system is analyzed, the required total WIP level of the system is estimated by using the neural networks, and then the total number of WIP is allocated to each workstation and operation by using the queuing theory to achieve the best overall throughput performance. The resulting WIP level for each workstation is then used to control the manufacturing system. Based on the difference between the planned and the actual WIP levels of different machines, an efficient control method is then developed to maintain robustness of the system.
The simulation result shown that the proposed method for allocating total WIP to workstations and operations can reduce 16% of mean cycle time and not increase the variation of cycle time in this manufacturing system.

[1]Rose, O., “CONLOAD – A New Lot Release Rule for Semiconductor Wafer Fabs,” Proceeding of the Winter Simulation Conference’ 99, pp. 850-855.
[2]Lee, Y. H. and Kim, T., “Manufacturing Cycle Time Reduction Using Balance Control in the Semiconductor Fabrication Line,” Production Planning & Control, vol. 13, no. 3, pp. 529-540, 2002.
[3]Enns, S. T., “An Integrated System for Controlling Shop Loading and Work Flow,” International Journal of Production Research, vol. 33, no. 10, pp. 2801-2820, 1995.
[4]Connors, D. P., Feigin, G. E. and Yao, D. D., “A Queueing Network Model for Semiconductor Manufacturing,” IEEE Transactions on Semiconductor Manufacturing, vol. 9, no. 3, pp. 412-427, 1996.
[5]Buzacott, J. A., “The Role of Banks in Flow-line Production Systems,” International Journal of Production Research, vol. 9, no. 4, pp. 425-436, 1971.
[6]Crandall, R. E. and Burwell, T. H., “The Effect of Work-In-Process Inventory Levels on Throughput and Lead Time,” Production and Inventory Management Journal, no. 1,pp. 6-12, 1993.
[7]Kumar, S. and Kumar, P. R., “Queueing Network Models in the Design and Analysis of Semiconductor Wafer Fabs,” IEEE Transactions on Robotics and Automation, vol. 17, no. 5, pp. 548-561, 2001.
[8]Lin, Y. H. and Lee, C. E., “A Total Standard WIP Estimation Method for Wafer Fabrication,” European Journal of Operation Research, vol. 131, no. 1, pp. 78-94, 2001.
[9]Gilland, W., “A Simulation Study Comparing Performance of CONWIP and Bottleneck-based Release Rule,” Production Planning & Control, vol. 13, no. 2, pp. 211-219, 2002.
[10]Ryan, S. M. and Choobineh, F. F., “Total WIP and WIP Mix for a CONWIP Controlled Job Shop,” IIE Transactions, vol. 35, no. 5, pp. 405-418, 2003.
[11]Wu, K., “An Examination of Variability and Its Basic Properties for a Factory,” IEEE Transactions on Semiconductor Manufacturing, vol. 18, no. 1, pp. 214-221, 2005.
[12]Hopp, W. J. and Spearman, M. L., Factory Physics: Foundations of Manufacturing. 2nded. UK: Irwin McGraw-Hill, 2001.
[13]Duri, C., Y. Frein, and Lee, H. S., “Performance Evaluation and Design of a CONWIP System with Inspections,” International Journal of Production Economics, vol. 64, pp. 219-229, 2000.
[14]Gstettner, S. and Kuhn, H., “Analysis of Production Control Systems Kanban and CONWIP,” International Journal of Production Research, vol. 34, no. 11, pp. 3253–3274, 1996.
[15]Hoop, W. J. and Spearman, M. L., “Throughput of a Constant Work in Process Manufacturing Line Subject to Failures,” International Journal of Production Research, vol. 29, no. 3, pp. 635-655, 1991.
[16]Ryan, S. M., Baynat, B. and Choobineh, F. F., “Determining Inventory Levels in a CONWIP Controlled Job Shop,” IIE Transaction, vol. 32, no. 2, pp. 105-114, 2000.
[17]Herer, Y. T. and Masin, M., “Mathematical Programming Formulation of CONWIP Based Production Lines and Relationships to MRP,” International Journal of Production Research, vol. 35, no. 4,pp. 1067–1076, 1997.
[18]Burman, D. Y., Gurrola-Gal, F. J., Nozari, A., Sathaye, S. and Sitarik, J. P., “Performance Analysis Techniques for IC Manufacturing Lines,” AT&T Technical Journal, vol. 65, no. 4, pp. 46-57, 1986.
[19]Bonvik, A. M., Couch, C. E. and Gershwin, S. B., “A Comparison of Production-line Control Mechanisms,” International Journal of Production Research, vol. 25, no.3, pp. 789-804, 1997.
[20]Duenyas, I. and Patananake, P., “Base-stock Control for Single Product Tandem Make-to-stock Systems,” IIE Transactions, vol. 30, no.1, pp. 31-39, 1998.
[21]Choobineh, F. and Sowrirajan, S., “Capacitated – Constant Work in Process (C-CONWIP): a Job Shop Control System.,” Technical report, Industrial and Management Systems Engineering, University of Nebraska, Lincoln, NE 68588-0518, USA, 1996.
[22]Luh, P. B., Zhou, X. and Tomastik, R. N., “An Effective Method to Reduce Inventory in Job Shops,” IEEE Transactions on Robotics and Automation, vol. 16, no. 4, pp. 420-424, 2000.
[23]Kim, S., Kim, Y. and Kim, B., “Stepper Scheduling in Semiconductor Wafer Fabrication Process,” The Proceedings of International Conference on Modeling and Analysis of Semiconductor Manufacturing, Arizona, pp. 151-156, 2000.
[24]Reinschmidt, K. F., “Neural Networks: Next Step for Simulation and Control,” Power Engineering, vol. 95, no. 11, pp. 41-45, Nov. 1991.
[25]Chambers, M. and Mount-Campbell, C. A., “Process Optimization via Neural Network Metamodeling,” International Journal Production Economics, vol. 79, pp. 93-10, 2002.
[26]Stokes, D., and May, G.S., “Indirect Adaptive Control of Reactive Ion Etching Using Neural Networks,” IEEE Transactions on Robotics and Automation, vol. 17, no. 5, pp. 650-657, 2001.
[27]Huang, Y.L., Edgar, T.F., Himmelblau, D.M.,and Trachtenberg, I., “Constructing a Reliable Neural Network Model for a Plasma Etching Process Using Limited Experimental Data,” IEEE Transactions on Semiconductor Manufacturing, vol. 7, no. 3, pp. 333-344, 1994.
[28]Cardarelli, G., Palumbo, M. and Pelagagge, M., “Use of Neural Networks in Modeling Relations between Exposure Energy and Pattern Dimension in Photolithography Process,” IEEE Transactions on Components, Packaging, and Manufacturing technology-Part C, vol. 19, no. 4, pp. 290-299, 1996.
[29]Natale, C.D., Proietti, E., Diamanti, R. and D’Amico, A., “Modeling of APCVD-Doped Silicon Dioxide Deposition Process by a Modular Neural Network”, IEEE Transactions on Semiconductor Manufacturing, vol. 12, no. 1, pp. 109-115, 1999.
[30]Schikora, P.F. and Godfrey, M.R., “Efficacy of End-user Neural Network and Data Mining Software for Predicting Complex System Performance,” International Journal of Production Economics, vol. 84, pp. 231-253, 2003.
[31]Liao, D.Y., and Wang, C.N., “Neural-Network-Based Delivery Time Estimates for Prioritized 300-mm Automatic Material Handling Operations,” IEEE Transactions on Semiconductor Manufacturing, vol. 17, no. 3, pp. 324-332, 2004.
[32]Yu, C.Y. and Huang, H.P., “On-Line Learning Delivery Decision Support System for Highly Product Mixed Semiconductor Foundry,” IEEE Transactions on Semiconductor Manufacturing, vol. 15, no. 2, pp. 274-278, 2002.
[33]Roiger, R.J. and Geatz, M.W., Data mining: A Tutorial-based Primer. Addison-Wesley, 2003.
[34]Han, J. and Kamber, M., Data Mining: Concepts and Techniques. Morgan Kaufmann Publishers, 2001.
[35]Whitt, W., “Approximations for the GI/G/m Queue,” Production and Operations Management, vol. 2, no. 2, pp. 115-161, 1993.
[36]Li, S., Tang, T. and Collins, D. W., “Minimum Inventory Variability Schedule with Applications in Semiconductor Fabrication,” IEEE Transaction on Semiconductor Manufacturing, vol. 9, no. 1, pp. 145-149, 1996.