With the development of process technology, a lot of circuits can be integrated on chip. For digital circuit, clock-path mismatch will become an important issue. In order to improve the difference of wire delay, buffers inserted into the clock path aim to balance the path delay. Of course buffers cannot introduce additional jitter. In this thesis, a low jitter buffer was developed and it can reduce the jitter effectively. And in order to measure and verify the buffer on silicon, a full test chip was developed to compensate for I/O cell and loading delays for the most accurate timing measurement. This cell was also characterized to generate liberty file such that it can be included into the standard cell library for general usage. A good correlation between simulations and measurements was obtained.
　　In addition, non-ideal effect becomes more obvious when the device size decreases gradually. Recent studies showed that random telegraph signal　(RTS) noise is strongly correlated with excess leakage current in sub-micrometer MOS transistors. For circuit designers, the impact of this noise current cannot be ignored. This thesis also studies the time-domain jitter caused by RTS noise. A model, which describes the emission and capture of electrons in device channel region based on Poisson statistic, was developed and implemented in HSPICE. This model can be used to simulate circuits with RTS noise. Using this model, we build higher level expression for basic gate jitter behavior, and the results are comparable to simulated data.

隨著製程技術的演進，許多電路都可被整合到晶片內．而對於數位電路來說，時脈路徑的不匹配將會是一個重要考量．因此，為了改善導線延遲上的差異，許多緩衝器可被嵌入至時脈路徑中，以平衡路徑上的延遲問題．而這些被嵌入的緩衝器本身也不應該產生額外的信號抖動．本篇論文提出一個低信號抖動的緩衝器，可有效的降低本身信號抖動的問題．並且為了量測以及驗證實際芯片上緩衝器的效能，另外設計一組測試晶片，可抵銷輸出入埠與負載對芯片所造成的影響及延遲，以達到更精確的量測數據．另外，也對於此緩衝器做一特徵化並置入於標準元件庫內以方便使用．而所有的實際量測數據與模擬分析上的結果是相符的．
另外，隨著元件尺寸不斷的下降，非理想效應也變得越來越顯著．近年來許多的研究指出，次微米電晶體中所產生的漏電流與隨機電信訊號雜訊有著強烈的關係．而對於電路設計者來說，這樣的雜訊電流更是不能被忽略．本篇論文也詳細研究了受到隨機電信訊號雜訊所產生於時間域上的信號抖動．並且建構其模型，使得此效應可被用於Spice軟體上模擬分析．而此模型主要是根據Poisson統計學理論來描述元件通道內電子被捕獲及釋放的行為．並且利用此模型得出其數學式，可被用來解釋邏輯閘上的信號抖動，並且將其推導之結果與實際模擬數據做一詳細探討．

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